/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | misched-int-basic.mir | 61 # CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc,… 123 %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
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/external/llvm/test/MC/ARM/ |
D | mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.h | 166 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
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D | ARMScheduleSwift.td | 291 (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
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D | ARMISelDAGToDAG.cpp | 2945 case ARMISD::UMLAL:{ in Select() 2990 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
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D | ARMInstrInfo.td | 3944 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3975 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 5780 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5794 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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D | ARMISelLowering.cpp | 1219 case ARMISD::UMLAL: return "ARMISD::UMLAL"; in getTargetNodeName() 8891 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL() 8979 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL() 8982 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenMCPseudoLowering.inc | 223 TmpInst.setOpcode(ARM::UMLAL);
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D | ARMGenAsmWriter.inc | 1441 96990U, // UMLAL 4661 0U, // UMLAL 7102 // SMLAL, UMLAL
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.h | 200 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
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D | ARMScheduleSwift.td | 308 (instregex "SMLAL", "UMLAL", "SMLALBT",
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D | ARMScheduleR52.td | 280 "SMLAL", "UMLAL", "SMLALBT",
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D | ARMISelDAGToDAG.cpp | 2817 case ARMISD::UMLAL:{ in Select() 2831 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
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D | ARMInstrInfo.td | 4125 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4159 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 6096 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6110 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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D | ARMISelLowering.cpp | 1348 case ARMISD::UMLAL: return "ARMISD::UMLAL"; in getTargetNodeName() 10144 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL() 10251 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL() 10254 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL() 12755 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
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D | ARMScheduleA9.td | 2552 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
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/external/llvm/lib/Target/AArch64/ |
D | AArch64SchedCyclone.td | 523 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64SchedCyclone.td | 525 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
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/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 3877 ### UMLAL ### subsection 3887 ### UMLAL ### subsection
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/external/capstone/arch/ARM/ |
D | ARMGenAsmWriter.inc | 511 92184U, // UMLAL 3304 0U, // UMLAL 6181 // SMLAL, UMLAL 9214 // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 2115 # UMLAL
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D | thumb2.txt | 2277 # UMLAL
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 2288 # UMLAL
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D | thumb2.txt | 2428 # UMLAL
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