| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | icmp-mul-zext.ll | 89 ; CHECK-NEXT: [[UMUL:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A:%.*]], i16 [[…
90 ; CHECK-NEXT: [[UMUL_VALUE:%.*]] = extractvalue { i16, i1 } [[UMUL]], 0
91 ; CHECK-NEXT: [[DID_OVF:%.*]] = extractvalue { i16, i1 } [[UMUL]], 1
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| /external/mesa3d/src/gallium/tests/graw/vertex-shader/ |
| D | vert-imul_hi.sh | 11 UMUL TEMP[0], TEMP[0], IMM[0].wwww
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 143 OP12(UMUL)
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| D | tgsi_info_opcodes.h | 136 OPCODE(1, 2, COMP, UMUL)
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 171 OP12(UMUL)
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 223 UMUL, // 32bit unsigned multiplication enumerator
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| D | AMDGPUISelLowering.cpp | 2799 NODE_NAME_CASE(UMUL); in getTargetNodeName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 316 UMUL, // 32bit unsigned multiplication enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 240 UMUL, // LOW, HI, FLAGS = umul LHS, RHS enumerator
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| D | X86ISelDAGToDAG.cpp | 1834 case X86ISD::UMUL: { in Select()
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| D | X86ISelLowering.cpp | 8602 Opc == X86ISD::UMUL || in isX86LogicalCmp()
8610 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) in isX86LogicalCmp()
8793 Cond.getOpcode() == X86ISD::UMUL) in LowerBRCOND()
10094 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); in LowerXALUO()
10702 case X86ISD::UMUL: return "X86ISD::UMUL"; in getTargetNodeName()
12319 case X86ISD::UMUL: in computeMaskedBitsForTargetNode()
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| D | X86InstrInfo.td | 214 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 349 UMUL, enumerator
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| D | X86FastISel.cpp | 2742 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2782 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
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| D | X86ISelDAGToDAG.cpp | 2133 case X86ISD::UMUL: { in Select()
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| D | X86ISelLowering.cpp | 15687 Opc == X86ISD::UMUL || in isX86LogicalCmp()
15695 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) in isX86LogicalCmp()
15917 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
16563 Cond.getOpcode() == X86ISD::UMUL) in LowerBRCOND()
16627 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
20528 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); in LowerXALUO()
22207 case X86ISD::UMUL: return "X86ISD::UMUL"; in getTargetNodeName()
24622 case X86ISD::UMUL: in computeKnownBitsForTargetNode()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 194 #define UMUL (OPC1(0x2) | OPC3(0x0a)) macro
818 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? UMUL : SMUL) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(… in sljit_emit_op0()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 359 UMUL, enumerator
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| D | X86FastISel.cpp | 2925 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2965 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
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| D | X86ISelDAGToDAG.cpp | 2919 case X86ISD::UMUL: { in Select()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 489 defm UMUL : F3_12np<"umul", 0b001010>;
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 700 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL); in get_opcode()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 741 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 737 defm UMUL : F3_12np<"umul", 0b001010, IIC_iu_umul>;
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 886 NV50_IR_OPCODE_CASE(UMUL, MUL); in translateOpcode()
|