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Searched refs:getLocVT (Results 1 – 25 of 65) sorted by relevance

123

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2ISelLowering.cpp54 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) in LowerReturn()
55 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); in LowerReturn()
61 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
110 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
140 MVT LocVT = VA.getLocVT(); in LowerFormalArguments()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp185 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
211 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerFormalArguments()
260 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
263 Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
266 Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
317 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
320 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
323 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
335 assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type"); in LowerCall()
394 RVLocs[i].getLocVT(), InFlag); in LowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp307 EVT LocVT = VA.getLocVT(); in LowerCCCArguments()
416 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
419 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
422 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
529 VA.getLocVT(), InFlag).getValue(1); in LowerCallResult()
537 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
540 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
589 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
591 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
593 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp238 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
323 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
326 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
329 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
417 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
445 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
452 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp240 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
253 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
325 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
331 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
357 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
418 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
444 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
451 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCISelLowering.cpp274 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
277 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
280 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
486 EVT RegVT = VA.getLocVT(); in LowerCallArguments()
503 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerCallArguments()
512 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCallArguments()
642 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerReturn()
670 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp1679 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
1681 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
1684 ArgVT = VA.getLocVT(); in DoSelectCall()
1688 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
1690 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
1693 ArgVT = VA.getLocVT(); in DoSelectCall()
1697 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
1699 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in DoSelectCall()
1702 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
1705 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp667 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
674 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
868 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
895 EVT LocVT = VA.getLocVT(); in unpackFromMemLoc()
920 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && in unpackF64OnRV32DSoftABI()
998 assert(VA.getLocVT() == XLenVT && "Unhandled argument type"); in LowerFormalArguments()
1002 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) in LowerFormalArguments()
1254 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
1289 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), ArgValue); in LowerCall()
1414 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CallLowering.cpp140 unsigned LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
155 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
262 unsigned LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
275 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
DX86FastISel.cpp3350 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3356 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3359 ArgVT = VA.getLocVT(); in fastLowerCall()
3363 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3376 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3379 ArgVT = VA.getLocVT(); in fastLowerCall()
3383 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3385 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3388 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3391 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
[all …]
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp174 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
203 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
279 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
282 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
285 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
262 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
337 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
340 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
343 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcISelLowering.cpp185 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments()
215 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments()
217 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments()
219 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments()
220 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments()
421 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
424 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
427 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
430 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
448 assert(VA.getLocVT() == MVT::f64); in LowerCall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DCallLowering.cpp158 LLT LocTy{VA.getLocVT()}; in extendRegister()
167 assert(!VA.getLocVT().isVector() && "unexpected vector extend"); in extendRegister()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp1593 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1597 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1601 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1605 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1609 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1612 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1615 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1619 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1623 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, in ProcessCallArgs()
1627 ArgVT = VA.getLocVT(); in ProcessCallArgs()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp326 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
361 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
364 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
373 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
479 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
482 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
485 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp436 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
479 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
482 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
492 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
539 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
591 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
594 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
597 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2722 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2794 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
2796 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
2797 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
2915 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
2921 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
2925 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
2926 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
2943 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
2949 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2980 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
3052 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
3054 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
3055 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
3209 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
3215 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
3219 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
3220 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
3237 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3243 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
492 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
496 << EVT(VA.getLocVT()).getEVTString() << "\n"; in LowerCCCArguments()
505 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
561 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
667 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
670 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
673 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp444 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
476 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
480 << EVT(VA.getLocVT()).getEVTString() << "\n"; in LowerCCCArguments()
489 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
546 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
655 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
658 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
661 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
274 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
366 VA.getLocVT(), InFlag).getValue(1); in LowerCallResult()
374 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
377 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp618 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
661 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
664 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
674 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
746 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
812 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
815 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
818 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp120 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
134 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
347 auto LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp3142 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3148 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3151 ArgVT = VA.getLocVT(); in fastLowerCall()
3155 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3168 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3171 ArgVT = VA.getLocVT(); in fastLowerCall()
3175 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3177 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3180 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3183 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
[all …]

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