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Searched refs:rk_clrsetreg (Results 1 – 25 of 40) sorted by relevance

12

/external/u-boot/drivers/pinctrl/rockchip/
Dpinctrl_rk3399.c27 rk_clrsetreg(&grf->gpio4c_iomux, in pinctrl_rk3399_pwm_config()
32 rk_clrsetreg(&grf->gpio4c_iomux, in pinctrl_rk3399_pwm_config()
37 rk_clrsetreg(&pmugrf->gpio1c_iomux, in pinctrl_rk3399_pwm_config()
43 rk_clrsetreg(&pmugrf->gpio1b_iomux, in pinctrl_rk3399_pwm_config()
47 rk_clrsetreg(&pmugrf->gpio0a_iomux, in pinctrl_rk3399_pwm_config()
63 rk_clrsetreg(&pmugrf->gpio1b_iomux, in pinctrl_rk3399_i2c_config()
66 rk_clrsetreg(&pmugrf->gpio1c_iomux, in pinctrl_rk3399_i2c_config()
72 rk_clrsetreg(&grf->gpio4a_iomux, in pinctrl_rk3399_i2c_config()
75 rk_clrsetreg(&grf->gpio4a_iomux, in pinctrl_rk3399_i2c_config()
81 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3399_i2c_config()
[all …]
Dpinctrl_rk3288.c126 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT, in pinctrl_rk3288_pwm_config()
130 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT, in pinctrl_rk3288_pwm_config()
134 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT, in pinctrl_rk3288_pwm_config()
138 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT, in pinctrl_rk3288_pwm_config()
161 rk_clrsetreg(&grf->gpio8a_iomux, in pinctrl_rk3288_i2c_config()
168 rk_clrsetreg(&grf->gpio6b_iomux, in pinctrl_rk3288_i2c_config()
175 rk_clrsetreg(&grf->gpio2c_iomux, in pinctrl_rk3288_i2c_config()
182 rk_clrsetreg(&grf->gpio7cl_iomux, in pinctrl_rk3288_i2c_config()
189 rk_clrsetreg(&grf->gpio7cl_iomux, in pinctrl_rk3288_i2c_config()
192 rk_clrsetreg(&grf->gpio7ch_iomux, in pinctrl_rk3288_i2c_config()
[all …]
Dpinctrl_rk3328.c286 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3328_pwm_config()
291 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3328_pwm_config()
296 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3328_pwm_config()
301 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3328_pwm_config()
315 rk_clrsetreg(&grf->gpio2d_iomux, in pinctrl_rk3328_i2c_config()
321 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3328_i2c_config()
327 rk_clrsetreg(&grf->gpio2bl_iomux, in pinctrl_rk3328_i2c_config()
333 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk3328_i2c_config()
370 rk_clrsetreg(&grf->gpio2bl_iomux, in pinctrl_rk3328_spi_config()
376 rk_clrsetreg(&grf->gpio2bl_iomux, in pinctrl_rk3328_spi_config()
[all …]
Dpinctrl_rk322x.c533 rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK, in pinctrl_rk322x_pwm_config()
536 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, in pinctrl_rk322x_pwm_config()
541 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK, in pinctrl_rk322x_pwm_config()
544 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK, in pinctrl_rk322x_pwm_config()
549 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, in pinctrl_rk322x_pwm_config()
552 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK, in pinctrl_rk322x_pwm_config()
557 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK, in pinctrl_rk322x_pwm_config()
560 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK, in pinctrl_rk322x_pwm_config()
573 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk322x_i2c_config()
580 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk322x_i2c_config()
[all …]
Dpinctrl_rk3188.c478 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT, in pinctrl_rk3188_pwm_config()
482 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT, in pinctrl_rk3188_pwm_config()
486 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT, in pinctrl_rk3188_pwm_config()
490 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT, in pinctrl_rk3188_pwm_config()
504 rk_clrsetreg(&grf->gpio1d_iomux, in pinctrl_rk3188_i2c_config()
510 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, in pinctrl_rk3188_i2c_config()
514 rk_clrsetreg(&grf->gpio1d_iomux, in pinctrl_rk3188_i2c_config()
519 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT, in pinctrl_rk3188_i2c_config()
523 rk_clrsetreg(&grf->gpio1d_iomux, in pinctrl_rk3188_i2c_config()
528 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT, in pinctrl_rk3188_i2c_config()
[all …]
Dpinctrl_rk3036.c436 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, in pinctrl_rk3036_pwm_config()
440 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK, in pinctrl_rk3036_pwm_config()
444 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK, in pinctrl_rk3036_pwm_config()
448 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK, in pinctrl_rk3036_pwm_config()
461 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk3036_i2c_config()
468 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk3036_i2c_config()
474 rk_clrsetreg(&grf->gpio2c_iomux, in pinctrl_rk3036_i2c_config()
487 rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK, in pinctrl_rk3036_spi_config()
491 rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK, in pinctrl_rk3036_spi_config()
495 rk_clrsetreg(&grf->gpio1d_iomux, in pinctrl_rk3036_spi_config()
[all …]
Dpinctrl_rk3128.c28 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk3128_i2c_config()
35 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk3128_i2c_config()
41 rk_clrsetreg(&grf->gpio2c_iomux2, in pinctrl_rk3128_i2c_config()
47 rk_clrsetreg(&grf->gpio0a_iomux, in pinctrl_rk3128_i2c_config()
60 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, in pinctrl_rk3128_sdmmc_config()
69 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3128_sdmmc_config()
75 rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff, in pinctrl_rk3128_sdmmc_config()
Dpinctrl_rk3368.c477 rk_clrsetreg(&grf->gpio2a_iomux, in pinctrl_rk3368_uart_config()
488 rk_clrsetreg(&pmugrf->gpio0d_iomux, in pinctrl_rk3368_uart_config()
514 rk_clrsetreg(&grf->gpio1d_iomux, in pinctrl_rk3368_spi_config()
519 rk_clrsetreg(&grf->gpio1c_iomux, in pinctrl_rk3368_spi_config()
528 rk_clrsetreg(&grf->gpio1b_iomux, in pinctrl_rk3368_spi_config()
531 rk_clrsetreg(&grf->gpio1c_iomux, in pinctrl_rk3368_spi_config()
536 rk_clrsetreg(&pmugrf->gpio0b_iomux, in pinctrl_rk3368_spi_config()
551 rk_clrsetreg(&grf->gpio3b_iomux, in pinctrl_rk3368_gmac_config()
558 rk_clrsetreg(&grf->gpio3c_iomux, in pinctrl_rk3368_gmac_config()
567 rk_clrsetreg(&grf->gpio3d_iomux, in pinctrl_rk3368_gmac_config()
[all …]
Dpinctrl_rv1108.c424 rk_clrsetreg(&grf->gpio3a_iomux, in pinctrl_rv1108_uart_config()
430 rk_clrsetreg(&grf->gpio1d_iomux, in pinctrl_rv1108_uart_config()
439 rk_clrsetreg(&grf->gpio2d_iomux, in pinctrl_rv1108_uart_config()
449 rk_clrsetreg(&grf->gpio1b_iomux, in pinctrl_rv1108_gmac_config()
458 rk_clrsetreg(&grf->gpio1c_iomux, in pinctrl_rv1108_gmac_config()
470 rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK | in pinctrl_rv1108_sfc_config()
476 rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK, in pinctrl_rv1108_sfc_config()
/external/u-boot/drivers/net/
Dgmac_rockchip.c98 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); in rk3228_gmac_fix_mac_speed()
124 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); in rk3288_gmac_fix_mac_speed()
157 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); in rk3328_gmac_fix_mac_speed()
189 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); in rk3368_gmac_fix_mac_speed()
215 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); in rk3399_gmac_fix_mac_speed()
248 rk_clrsetreg(&grf->gmac_con0, in rv1108_set_rmii_speed()
283 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_set_to_rgmii()
292 rk_clrsetreg(&grf->mac_con[0], in rk3228_gmac_set_to_rgmii()
304 rk_clrsetreg(&grf->soc_con1, in rk3288_gmac_set_to_rgmii()
308 rk_clrsetreg(&grf->soc_con3, in rk3288_gmac_set_to_rgmii()
[all …]
/external/u-boot/arch/arm/mach-rockchip/rk3368/
Drk3368.c71 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
73 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
75 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
77 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
79 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, in mcu_init()
81 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, in mcu_init()
84 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, in mcu_init()
/external/u-boot/drivers/clk/rockchip/
Dclk_rk3288.c161 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, in rkclk_set_pll()
163 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
164 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
204 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
214 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
324 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
346 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, in rockchip_vop_set_clk()
357 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, in rockchip_vop_set_clk()
363 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, in rockchip_vop_set_clk()
367 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, in rockchip_vop_set_clk()
[all …]
Dclk_rk322x.c62 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
86 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
106 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
111 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
129 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
134 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
154 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
163 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
263 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, in rk322x_mac_set_clk()
[all …]
Dclk_rk3188.c103 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
106 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
109 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
208 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
213 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
300 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
[all …]
Dclk_rk3399.c309 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
313 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, in rkclk_set_pll()
316 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, in rkclk_set_pll()
318 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
330 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
419 rk_clrsetreg(&cru->clksel_con[0], in rk3399_configure_cpu()
426 rk_clrsetreg(&cru->clksel_con[1], in rk3399_configure_cpu()
502 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), in rk3399_i2c_set_clk()
506 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), in rk3399_i2c_set_clk()
510 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), in rk3399_i2c_set_clk()
[all …]
Dclk_rk3328.c256 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); in rkclk_set_pll()
259 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK, in rkclk_set_pll()
262 rk_clrsetreg(&pll_con[0], in rkclk_set_pll()
266 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
294 rk_clrsetreg(&cru->clksel_con[28], in rkclk_init()
298 rk_clrsetreg(&cru->clksel_con[29], in rkclk_init()
317 rk_clrsetreg(&cru->clksel_con[0], in rk3328_configure_cpu()
322 rk_clrsetreg(&cru->clksel_con[1], in rk3328_configure_cpu()
367 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
[all …]
Dclk_rk3128.c59 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
147 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
167 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
172 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
190 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
195 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
215 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
224 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
231 rk_clrsetreg(&cru->cru_clksel_con[2], in rkclk_init()
[all …]
Dclk_rk3036.c64 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
67 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
85 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
105 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
110 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
133 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
153 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
162 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
260 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
[all …]
Dclk_rv1108.c103 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
124 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, in rv1108_sfc_set_clk()
150 rk_clrsetreg(&cru->clksel_con[22], in rv1108_saradc_set_clk()
204 rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, in rkclk_init()
Dclk_rk3368.c100 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
103 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, in rkclk_set_pll()
122 rk_clrsetreg(&pll->con3, PLL_MODE_MASK, in rkclk_set_pll()
273 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_mmc_set_clk()
340 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK, in rk3368_gmac_set_clk()
418 rk_clrsetreg(&cru->clksel_con[spiclk->reg], in rk3368_spi_set_clk()
445 rk_clrsetreg(&cru->clksel_con[25], in rk3368_saradc_set_clk()
/external/u-boot/arch/arm/mach-rockchip/
Drk3399-board-spl.c87 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
90 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
95 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
98 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
102 rk_clrsetreg(&grf->soc_con7, in board_debug_uart_init()
146 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); in board_init_f()
Drk322x-board.c55 rk_clrsetreg(&grf->gpio1b_iomux, in board_init()
60 rk_clrsetreg(&grf->con_iomux, in board_init()
68 rk_clrsetreg(&grf->macphy_con[0], in board_init()
Drk322x-board-spl.c52 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
57 rk_clrsetreg(&grf->con_iomux, in board_debug_uart_init()
/external/u-boot/drivers/video/rockchip/
Drk3288_mipi.c38 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
43 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
64 rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
69 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
75 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
Drk3399_mipi.c36 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
40 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
60 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
64 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); in rk_mipi_dphy_mode_set()
68 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); in rk_mipi_dphy_mode_set()

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