| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | armv8.1a-rdma.s | 6 sqrdmlah v0.4h, v1.4h, v2.4h
8 sqrdmlah v0.2s, v1.2s, v2.2s
10 sqrdmlah v0.4s, v1.4s, v2.4s
12 sqrdmlah v0.8h, v1.8h, v2.8h
23 sqrdmlah v0.2h, v1.2h, v2.2h
27 sqrdmlah v0.8s, v1.8s, v2.8s
35 sqrdmlah v0.2s, v1.4h, v2.8h
41 sqrdmlah h0, h1, h2
43 sqrdmlah s0, s1, s2
51 sqrdmlah v0.4h, v1.4h, v2.h[3]
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-rdma.s | 6 sqrdmlah v0.4h, v1.4h, v2.4h
8 sqrdmlah v0.2s, v1.2s, v2.2s
10 sqrdmlah v0.4s, v1.4s, v2.4s
12 sqrdmlah v0.8h, v1.8h, v2.8h
23 sqrdmlah v0.2h, v1.2h, v2.2h
25 sqrdmlah v0.8s, v1.8s, v2.8s
27 sqrdmlah v0.2s, v1.4h, v2.8h
67 sqrdmlah h0, h1, h2
69 sqrdmlah s0, s1, s2
77 sqrdmlah v0.4h, v1.4h, v2.h[3]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-rdma.txt | 3 [0x20,0x84,0x02,0x2e] # sqrdmlah v0.8b, v1.8b, v2.8b
5 [0x20,0x84,0xc2,0x2e] # sqrdmlah v0.1d, v1.1d, v2.1d
7 [0x20,0x84,0x02,0x6e] # sqrdmlah v0.16b, v1.16b, v2.16b
9 [0x20,0x84,0xc2,0x6e] # sqrdmlah v0.2d, v1.2d, v2.2d
28 [0x20,0x84,0x02,0x7e] # sqrdmlah b0, b1, b2
30 [0x20,0x84,0xc2,0x7e] # sqrdmlah d0, d1, d2
41 [0x20,0xd0,0x32,0x2f] # sqrdmlah v0.8b, v1.8b, v2.b[3]
43 [0x20,0xd0,0xe2,0x2f] # sqrdmlah v0.1d, v1.1d, v2.d[1]
45 [0x20,0xd0,0x32,0x6f] # sqrdmlah v0.16b, v1.16b, v2.b[3]
47 [0x20,0xd8,0xe2,0x6f] # sqrdmlah v0.2d, v1.2d, v2.d[3]
[all …]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-rdma.txt | 3 [0x20,0x84,0x02,0x2e] # sqrdmlah v0.8b, v1.8b, v2.8b
5 [0x20,0x84,0xc2,0x2e] # sqrdmlah v0.1d, v1.1d, v2.1d
7 [0x20,0x84,0x02,0x6e] # sqrdmlah v0.16b, v1.16b, v2.16b
9 [0x20,0x84,0xc2,0x6e] # sqrdmlah v0.2d, v1.2d, v2.2d
28 [0x20,0x84,0x02,0x7e] # sqrdmlah b0, b1, b2
30 [0x20,0x84,0xc2,0x7e] # sqrdmlah d0, d1, d2
41 [0x20,0xd0,0x32,0x2f] # sqrdmlah v0.8b, v1.8b, v2.b[3]
43 [0x20,0xd0,0xe2,0x2f] # sqrdmlah v0.1d, v1.1d, v2.d[1]
45 [0x20,0xd0,0x32,0x6f] # sqrdmlah v0.16b, v1.16b, v2.b[3]
47 [0x20,0xd8,0xe2,0x6f] # sqrdmlah v0.2d, v1.2d, v2.d[3]
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-v8.1a.ll | 35 ; CHECK-V81a: sqrdmlah v0.4h, v1.4h, v2.4h
36 ; CHECK-V81a-apple: sqrdmlah.4h v0, v1, v2
45 ; CHECK-V81a: sqrdmlah v0.8h, v1.8h, v2.8h
46 ; CHECK-V81a-apple: sqrdmlah.8h v0, v1, v2
55 ; CHECK-V81a: sqrdmlah v0.2s, v1.2s, v2.2s
56 ; CHECK-V81a-apple: sqrdmlah.2s v0, v1, v2
65 ; CHECK-V81a: sqrdmlah v0.4s, v1.4s, v2.4s
66 ; CHECK-V81a-apple: sqrdmlah.4s v0, v1, v2
121 ; CHECK-V81a: sqrdmlah v0.4h, v1.4h, v2.h[3]
122 ; CHECK-V81a-apple: sqrdmlah.4h v0, v1, v2[3]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-v8.1a.ll | 38 ; CHECK-V81a: sqrdmlah v0.4h, v1.4h, v2.4h
39 ; CHECK-V81a-apple: sqrdmlah.4h v0, v1, v2
48 ; CHECK-V81a: sqrdmlah v0.8h, v1.8h, v2.8h
49 ; CHECK-V81a-apple: sqrdmlah.8h v0, v1, v2
58 ; CHECK-V81a: sqrdmlah v0.2s, v1.2s, v2.2s
59 ; CHECK-V81a-apple: sqrdmlah.2s v0, v1, v2
68 ; CHECK-V81a: sqrdmlah v0.4s, v1.4s, v2.4s
69 ; CHECK-V81a-apple: sqrdmlah.4s v0, v1, v2
124 ; CHECK-V81a: sqrdmlah v0.4h, v1.4h, v2.h[3]
125 ; CHECK-V81a-apple: sqrdmlah.4h v0, v1, v2[3]
[all …]
|
| /external/vixl/test/aarch64/ |
| D | test-cpu-features-aarch64.cc | 3354 TEST_RDM_NEON(sqrdmlah_0, sqrdmlah(v0.V4H(), v1.V4H(), v2.H(), 5))
3355 TEST_RDM_NEON(sqrdmlah_1, sqrdmlah(v0.V8H(), v1.V8H(), v2.H(), 4))
3356 TEST_RDM_NEON(sqrdmlah_2, sqrdmlah(v0.V2S(), v1.V2S(), v2.S(), 3))
3357 TEST_RDM_NEON(sqrdmlah_3, sqrdmlah(v0.V4S(), v1.V4S(), v2.S(), 0))
3358 TEST_RDM_NEON(sqrdmlah_4, sqrdmlah(h0, h1, v2.H(), 5))
3359 TEST_RDM_NEON(sqrdmlah_5, sqrdmlah(s0, s1, v2.S(), 1))
3360 TEST_RDM_NEON(sqrdmlah_6, sqrdmlah(v0.V4H(), v1.V4H(), v2.V4H()))
3361 TEST_RDM_NEON(sqrdmlah_7, sqrdmlah(v0.V8H(), v1.V8H(), v2.V8H()))
3362 TEST_RDM_NEON(sqrdmlah_8, sqrdmlah(v0.V2S(), v1.V2S(), v2.V2S()))
3363 TEST_RDM_NEON(sqrdmlah_9, sqrdmlah(v0.V4S(), v1.V4S(), v2.V4S()))
[all …]
|
| D | test-simulator-aarch64.cc | 4577 DEFINE_TEST_NEON_3SAME_HS(sqrdmlah, Basic)
4626 DEFINE_TEST_NEON_3SAME_SCALAR_HS(sqrdmlah, Basic)
4885 DEFINE_TEST_NEON_BYELEMENT(sqrdmlah, Basic, Basic, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
4906 DEFINE_TEST_NEON_BYELEMENT_SCALAR(sqrdmlah, Basic, Basic, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 4485 sqrdmlah(vf, rd, rn, rm); in VisitNEON3SameExtra()
4796 Op = &Simulator::sqrdmlah; in VisitNEONByIndexedElement()
5900 sqrdmlah(vf, rd, rn, rm); in VisitNEONScalar3SameExtra()
5945 Op = &Simulator::sqrdmlah; in VisitNEONScalarByIndexedElement()
|
| D | simulator-aarch64.h | 2116 LogicVRegister sqrdmlah(VectorFormat vform,
2732 LogicVRegister sqrdmlah(VectorFormat vform,
|
| D | assembler-aarch64.h | 3304 void sqrdmlah(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3333 void sqrdmlah(const VRegister& vd,
|
| D | logic-aarch64.cc | 906 LogicVRegister Simulator::sqrdmlah(VectorFormat vform, in sqrdmlah() function in vixl::aarch64::Simulator
913 return sqrdmlah(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqrdmlah()
3449 LogicVRegister Simulator::sqrdmlah(VectorFormat vform, in sqrdmlah() function in vixl::aarch64::Simulator
|
| D | macro-assembler-aarch64.h | 2608 V(sqrdmlah, Sqrdmlah) \
2786 V(sqrdmlah, Sqrdmlah) \
|
| D | assembler-aarch64.cc | 3566 void Assembler::sqrdmlah(const VRegister& vd, in sqrdmlah() function in vixl::aarch64::Assembler
3964 V(sqrdmlah, NEON_SQRDMLAH_byelement) \
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11907 "sqincw\005sqneg\010sqrdmlah\010sqrdmlsh\010sqrdmulh\006sqrshl\007sqrshr"
16519 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv1i16, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_…
16520 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv1i32, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_…
16521 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHi16_indexed, Convert__FPRAsmOperandFPR161_0__Tie0_1_1__FPR…
16522 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHi32_indexed, Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPR…
16523 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv4i32, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2…
16524 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv8i16, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2…
16525 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv2i32, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__…
16526 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv4i16, Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__…
16527 …{ 4211 /* sqrdmlah */, AArch64::SQRDMLAHv4i32_indexed, Convert__VectorReg1281_0__Tie0_1_1__VectorR…
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3025 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
3279 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
4656 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3297 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
3556 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
4991 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
|