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Searched refs:v32i16 (Results 1 – 25 of 70) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td89 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
94 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
98 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
104 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
107 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
108 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
109 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
110 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
111 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
114 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
[all …]
DX86TargetTransformInfo.cpp294 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
295 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
296 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
297 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
453 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw in getArithmeticInstrCost()
454 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
455 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw in getArithmeticInstrCost()
873 { TTI::SK_Broadcast, MVT::v32i16, 1 }, // vpbroadcastw in getShuffleCost()
876 { TTI::SK_Reverse, MVT::v32i16, 1 }, // vpermw in getShuffleCost()
880 { TTI::SK_PermuteSingleSrc, MVT::v32i16, 1 }, // vpermw in getShuffleCost()
[all …]
DX86CallingConv.td121 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
550 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
673 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
731 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
748 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
767 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-64b.ll16 %t0 = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a0)
45 %t0 = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a0)
92 %t0 = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a0)
114 declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>) #0
118 declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>) #0
122 declare <32 x i16> @llvm.cttz.v32i16(<32 x i16>) #0
Dbswap.ll8 %v0 = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %a0)
39 declare <32 x i16> @llvm.bswap.v32i16(<32 x i16>) #0
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h83 v32i16 = 35, // 32 x i16 enumerator
266 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
339 case v32i16: in getVectorElementType()
386 case v32i16: in getVectorNumElements()
498 case v32i16: in getSizeInBits()
619 if (NumElements == 32) return MVT::v32i16; in getVectorVT()
DValueTypes.td60 def v32i16 : ValueType<512, 35>; // 32 x i16 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td86 CCIfType<[v16i32,v32i16,v64i8],
92 CCIfType<[v16i32,v32i16,v64i8],
118 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsicsV60.td32 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
33 (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
41 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
42 (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h86 v32i16 = 38, // 32 x i16 enumerator
370 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
456 case v32i16: in getVectorElementType()
534 case v32i16: in getVectorNumElements()
729 case v32i16: in getSizeInBits()
860 if (NumElements == 32) return MVT::v32i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-masked_memop-16-8.ll73 …%res = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* %addr, i32 4, <32 x i1>%mask,…
76 declare <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>*, i32, <32 x i1>, <32 x i16>)
149 …call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> %val, <32 x i16>* %addr, i32 4, <32 x i1>%…
153 declare void @llvm.masked.store.v32i16.p0v32i16(<32 x i16>, <32 x i16>*, i32, <32 x i1>)
Dbitcast-setcc-512.ll8 define i32 @v32i16(<32 x i16> %a, <32 x i16> %b) {
9 ; SSE-LABEL: v32i16:
23 ; AVX1-LABEL: v32i16:
42 ; AVX2-LABEL: v32i16:
52 ; AVX512F-LABEL: v32i16:
67 ; AVX512BW-LABEL: v32i16:
Dbitcast-and-setcc-512.ll225 define i32 @v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32 x i16> %d) {
226 ; SSE-LABEL: v32i16:
252 ; AVX1-LABEL: v32i16:
283 ; AVX2-LABEL: v32i16:
304 ; AVX512F-LABEL: v32i16:
325 ; AVX512BW-LABEL: v32i16:
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/X86/
Dctlz.ll103 declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>, i1)
564 …estimated cost of 80 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
568 …estimated cost of 56 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
572 …estimated cost of 60 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
576 …estimated cost of 28 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
580 …estimated cost of 28 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
584 …estimated cost of 18 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
588 … estimated cost of 8 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
591 %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 0)
597 …estimated cost of 80 for instruction: %ctlz = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a, i1 …
[all …]
Dctpop.ll83 declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>)
284 …an estimated cost of 52 for instruction: %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
288 …an estimated cost of 36 for instruction: %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
292 …an estimated cost of 40 for instruction: %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
296 …an estimated cost of 18 for instruction: %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
300 …an estimated cost of 18 for instruction: %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
304 … an estimated cost of 9 for instruction: %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
307 %ctpop = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a)
Dcttz.ll102 declare <32 x i16> @llvm.cttz.v32i16(<32 x i16>, i1)
499 …estimated cost of 64 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
503 …estimated cost of 48 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
507 …estimated cost of 52 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
511 …estimated cost of 24 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
515 …estimated cost of 24 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
519 …estimated cost of 12 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
522 %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 0)
528 …estimated cost of 64 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
532 …estimated cost of 48 for instruction: %cttz = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a, i1 …
[all …]
Dbitreverse.ll106 declare <32 x i16> @llvm.bitreverse.v32i16(<32 x i16>)
339 …d cost of 108 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
343 …ed cost of 20 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
347 …ed cost of 24 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
351 …ed cost of 10 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
355 …ed cost of 10 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
359 …ted cost of 5 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
363 …ted cost of 8 for instruction: %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
366 %bitreverse = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
/external/llvm/lib/Target/X86/
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
671 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
677 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp164 case MVT::v32i16: return "v32i16"; in getEVTString()
245 case MVT::v32i16: return VectorType::get(Type::getInt16Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp167 case MVT::v32i16: return "v32i16"; in getEVTString()
245 case MVT::v32i16: return VectorType::get(Type::getInt16Ty(Context), 32); in getTypeForEVT()
/external/llvm/test/CodeGen/X86/
Dvector-popcnt-512.ll138 %out = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %in)
178 declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>)
Dvector-lzcnt-512.ll69 %out = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %in, i1 0)
101 %out = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %in, i1 -1)
219 declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>, i1)
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc106 if (RetVT.SimpleTy != MVT::v32i16)
184 case MVT::v32i16: return fastEmit_ISD_ABS_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
564 if (RetVT.SimpleTy != MVT::v32i16)
636 case MVT::v32i16: return fastEmit_ISD_CTPOP_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
1627 case MVT::v32i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i16_r(Op0, Op0IsKill);
2079 case MVT::v32i16: return fastEmit_ISD_TRUNCATE_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
2430 if (RetVT.SimpleTy != MVT::v32i16)
2553 case MVT::v32i16: return fastEmit_X86ISD_COMPRESS_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
3417 if (RetVT.SimpleTy != MVT::v32i16)
3540 case MVT::v32i16: return fastEmit_X86ISD_EXPAND_MVT_v32i16_r(RetVT, Op0, Op0IsKill);
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
412 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || in RetCC_Hexagon()
543 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
902 VT == MVT::v32i16 || VT == MVT::v64i8); in getIndexedAddressParts()
1119 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1756 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2873 case MVT::v32i16: in getRegForInlineAsmConstraint()
2884 case MVT::v32i16: in getRegForInlineAsmConstraint()
3031 case MVT::v32i16: in allowsMisalignedMemoryAccesses()
[all …]
DHexagonIntrinsicsV60.td89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
109 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
110 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),

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