1; This test checks that when SSE instructions access memory and require full 2; alignment, memory operands are limited to properly aligned stack operands. 3; This would only happen when we fuse a load instruction with another 4; instruction, which currently only happens with non-scalarized Arithmetic 5; instructions. 6 7; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s 8; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s 9 10; RUN: %if --need=target_MIPS32 --need=allow_dump \ 11; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ 12; RUN: -i %s --args -O2 \ 13; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 14; RUN: --command FileCheck --check-prefix MIPS32 %s 15 16define internal <4 x i32> @test_add(i32 %addr_i, <4 x i32> %addend) { 17entry: 18 %addr = inttoptr i32 %addr_i to <4 x i32>* 19 %loaded = load <4 x i32>, <4 x i32>* %addr, align 4 20 %result = add <4 x i32> %addend, %loaded 21 ret <4 x i32> %result 22} 23; CHECK-LABEL: test_add 24; CHECK-NOT: paddd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 25; CHECK: paddd xmm{{.}}, 26 27; MIPS32-LABEL: test_add 28; MIPS32: addu 29; MIPS32: addu 30; MIPS32: addu 31; MIPS32: addu 32 33define internal <4 x i32> @test_and(i32 %addr_i, <4 x i32> %addend) { 34entry: 35 %addr = inttoptr i32 %addr_i to <4 x i32>* 36 %loaded = load <4 x i32>, <4 x i32>* %addr, align 4 37 %result = and <4 x i32> %addend, %loaded 38 ret <4 x i32> %result 39} 40; CHECK-LABEL: test_and 41; CHECK-NOT: pand xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 42; CHECK: pand xmm{{.}}, 43 44; MIPS32-LABEL: test_and 45; MIPS32: and 46; MIPS32: and 47; MIPS32: and 48; MIPS32: and 49 50define internal <4 x i32> @test_or(i32 %addr_i, <4 x i32> %addend) { 51entry: 52 %addr = inttoptr i32 %addr_i to <4 x i32>* 53 %loaded = load <4 x i32>, <4 x i32>* %addr, align 4 54 %result = or <4 x i32> %addend, %loaded 55 ret <4 x i32> %result 56} 57; CHECK-LABEL: test_or 58; CHECK-NOT: por xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 59; CHECK: por xmm{{.}}, 60 61; MIPS32-LABEL: test_or 62; MIPS32: or 63; MIPS32: or 64; MIPS32: or 65; MIPS32: or 66 67define internal <4 x i32> @test_xor(i32 %addr_i, <4 x i32> %addend) { 68entry: 69 %addr = inttoptr i32 %addr_i to <4 x i32>* 70 %loaded = load <4 x i32>, <4 x i32>* %addr, align 4 71 %result = xor <4 x i32> %addend, %loaded 72 ret <4 x i32> %result 73} 74; CHECK-LABEL: test_xor 75; CHECK-NOT: pxor xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 76; CHECK: pxor xmm{{.}}, 77 78; MIPS32-LABEL: test_xor 79; MIPS32: xor 80; MIPS32: xor 81; MIPS32: xor 82; MIPS32: xor 83 84define internal <4 x i32> @test_sub(i32 %addr_i, <4 x i32> %addend) { 85entry: 86 %addr = inttoptr i32 %addr_i to <4 x i32>* 87 %loaded = load <4 x i32>, <4 x i32>* %addr, align 4 88 %result = sub <4 x i32> %addend, %loaded 89 ret <4 x i32> %result 90} 91; CHECK-LABEL: test_sub 92; CHECK-NOT: psubd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 93; CHECK: psubd xmm{{.}}, 94 95; MIPS32-LABEL: test_sub 96; MIPS32: subu 97; MIPS32: subu 98; MIPS32: subu 99; MIPS32: subu 100 101define internal <4 x float> @test_fadd(i32 %addr_i, <4 x float> %addend) { 102entry: 103 %addr = inttoptr i32 %addr_i to <4 x float>* 104 %loaded = load <4 x float>, <4 x float>* %addr, align 4 105 %result = fadd <4 x float> %addend, %loaded 106 ret <4 x float> %result 107} 108; CHECK-LABEL: test_fadd 109; CHECK-NOT: addps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 110; CHECK: addps xmm{{.}}, 111 112; MIPS32-LABEL: test_fadd 113; MIPS32: add.s 114; MIPS32: add.s 115; MIPS32: add.s 116; MIPS32: add.s 117 118define internal <4 x float> @test_fsub(i32 %addr_i, <4 x float> %addend) { 119entry: 120 %addr = inttoptr i32 %addr_i to <4 x float>* 121 %loaded = load <4 x float>, <4 x float>* %addr, align 4 122 %result = fsub <4 x float> %addend, %loaded 123 ret <4 x float> %result 124} 125; CHECK-LABEL: test_fsub 126; CHECK-NOT: subps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}} 127; CHECK: subps xmm{{.}}, 128 129; MIPS32-LABEL: test_fsub 130; MIPS32: sub.s 131; MIPS32: sub.s 132; MIPS32: sub.s 133; MIPS32: sub.s 134