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Searched refs:BL2_BASE (Results 1 – 25 of 32) sorted by relevance

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/external/arm-trusted-firmware/include/plat/arm/css/common/
Dcss_def.h178 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
179 #define SCP_BL2_LIMIT BL2_BASE
181 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
182 #define SCP_BL2U_LIMIT BL2_BASE
/external/arm-trusted-firmware/plat/layerscape/board/ls1043/include/
Dplatform_def.h109 #define BL2_BASE (BL31_BASE + BL31_TEXT_RODATA_SIZE) macro
110 #define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
116 #define BL2_BASE LS_BL2_DDR_BASE macro
117 #define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
/external/arm-trusted-firmware/include/plat/common/
Dcommon_def.h40 .image_info.image_base = BL2_BASE, \
41 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\
44 .ep_info.pc = BL2_BASE, \
/external/arm-trusted-firmware/plat/renesas/rcar/include/
Dplatform_def.h113 #define BL2_BASE U(0xE6304000) macro
116 #define BL2_BASE U(0xE6344000) macro
119 #define BL2_BASE U(0xE6304000) macro
122 #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/external/arm-trusted-firmware/bl2/
Dbl2.ld.S16 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
22 . = BL2_BASE;
Dbl2_el3.ld.S20 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
35 . = BL2_BASE;
/external/arm-trusted-firmware/include/plat/arm/common/
Darm_def.h383 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
391 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
420 #define BL31_PROGBITS_LIMIT BL2_BASE
426 #define BL31_LIMIT BL2_BASE
447 # define BL32_PROGBITS_LIMIT BL2_BASE
511 #define BL2U_BASE BL2_BASE
/external/arm-trusted-firmware/include/drivers/arm/css/
Dcss_scp.h45 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
46 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
/external/arm-trusted-firmware/plat/hisilicon/poplar/include/
Dpoplar_layout.h125 #define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET) macro
126 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
/external/arm-trusted-firmware/plat/socionext/uniphier/include/
Dplatform_def.h53 #define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) macro
54 #define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
/external/arm-trusted-firmware/plat/hisilicon/hikey960/include/
Dplatform_def.h61 #define BL2_BASE (0x1AC00000) macro
62 #define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
/external/arm-trusted-firmware/bl1/tbbr/
Dtbbr_img_desc.c18 .image_info.image_base = BL2_BASE,
19 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,
/external/arm-trusted-firmware/plat/hisilicon/poplar/
Dbl1_plat_setup.c52 bl2_tzram_layout.total_base = BL2_BASE; in bl1_plat_handle_post_image_load()
53 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; in bl1_plat_handle_post_image_load()
/external/arm-trusted-firmware/drivers/arm/css/scp/
Dcss_bom_bootloader.c56 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
57 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
/external/arm-trusted-firmware/plat/intel/soc/stratix10/
Dbl2_plat_setup.c87 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
/external/arm-trusted-firmware/plat/intel/soc/agilex/
Dbl2_plat_setup.c89 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
/external/arm-trusted-firmware/plat/arm/board/fvp_ve/include/
Dplatform_def.h201 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE) macro
210 #define BL32_PROGBITS_LIMIT BL2_BASE
/external/arm-trusted-firmware/plat/arm/board/a5ds/include/
Dplatform_def.h218 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE) macro
226 #define BL32_PROGBITS_LIMIT BL2_BASE
/external/arm-trusted-firmware/plat/hisilicon/hikey/include/
Dhikey_layout.h63 #define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ macro
/external/arm-trusted-firmware/include/plat/marvell/a3700/common/
Dmarvell_def.h159 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) macro
/external/arm-trusted-firmware/bl2/aarch64/
Dbl2_el3_entrypoint.S21 #define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE))
/external/arm-trusted-firmware/include/plat/marvell/a8k/common/
Dmarvell_def.h164 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) macro
/external/arm-trusted-firmware/plat/imx/imx7/picopi/include/
Dplatform_def.h118 #define BL2_BASE BL2_RAM_BASE macro
/external/arm-trusted-firmware/plat/imx/imx7/warp7/include/
Dplatform_def.h121 #define BL2_BASE BL2_RAM_BASE macro
/external/arm-trusted-firmware/plat/socionext/uniphier/
Duniphier_bl2_setup.c46 uniphier_mem_base += BL_CODE_BASE - BL2_BASE; in bl2_el3_plat_arch_setup()

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