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Searched refs:CONFIG_ROCKCHIP_STIMER_BASE (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/arch/arm/mach-rockchip/
Dtpl.c25 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
35 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
36 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); in rockchip_stimer_init()
37 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); in rockchip_stimer_init()
38 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + in rockchip_stimer_init()
Drk3036-board-spl.c24 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
25 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); in rockchip_stimer_init()
26 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); in rockchip_stimer_init()
27 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + in rockchip_stimer_init()
Dpx30-board-tpl.c28 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in secure_timer_init()
29 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0); in secure_timer_init()
30 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1); in secure_timer_init()
32 CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in secure_timer_init()
Dspl.c76 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
84 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
85 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); in rockchip_stimer_init()
86 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); in rockchip_stimer_init()
87 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + in rockchip_stimer_init()
/external/u-boot/arch/arm/mach-rockchip/rk3399/
Drk3399.c67 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
72 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L); in rockchip_stimer_init()
73 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H); in rockchip_stimer_init()
74 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L); in rockchip_stimer_init()
75 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H); in rockchip_stimer_init()
76 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \ in rockchip_stimer_init()
/external/u-boot/include/configs/
Drk3368_common.h22 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 macro
Drk322x_common.h15 #define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 macro
Drk3036_common.h14 #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 macro
Drk3328_common.h13 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 macro
Drk3128_common.h16 #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 macro
Drk3288_common.h17 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 macro
Dpx30_common.h16 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 macro
Drk3308_common.h25 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 macro
Drk3399_common.h15 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 macro
/external/u-boot/scripts/
Dconfig_whitelist.txt1477 CONFIG_ROCKCHIP_STIMER_BASE