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Searched refs:CONFIG_SYS_DDR_TIMING_0 (Results 1 – 25 of 52) sorted by relevance

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/external/u-boot/include/configs/km/
Dkm-mpc8360.h53 #define CONFIG_SYS_DDR_TIMING_0 (\ macro
Dkm-mpc832x.h57 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ macro
Dkm-mpc8309.h92 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ macro
/external/u-boot/board/freescale/p1_twr/
Dddr.c32 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, in fixed_sdram()
/external/u-boot/board/socrates/
Dsdram.c37 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/external/u-boot/board/mpc8308_p1m/
Dsdram.c46 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
/external/u-boot/board/freescale/mpc8308rdb/
Dsdram.c50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
/external/u-boot/board/gdsys/mpc8308/
Dsdram.c53 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
/external/u-boot/include/configs/
Dsocrates.h82 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 macro
Dmpc8308_p1m.h65 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
DMPC8308RDB.h61 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
DMPC832XEMDS.h40 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
Dve8313.h53 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
DMPC8323ERDB.h40 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
Dids8313.h61 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ macro
DMPC8313ERDB_NOR.h76 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
DMPC8349EMDS.h79 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 macro
DMPC8313ERDB_NAND.h104 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
DMPC8349EMDS_SDRAM.h79 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 macro
DMPC837XEMDS.h69 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
/external/u-boot/board/freescale/mpc8315erdb/
Dsdram.c67 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/external/u-boot/board/freescale/mpc832xemds/
Dmpc832xemds.c137 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/external/u-boot/board/freescale/mpc8313erdb/
Dsdram.c76 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/external/u-boot/board/Arcturus/ucp1020/
Dddr.c92 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, in fixed_sdram()
/external/u-boot/board/freescale/mpc8641hpcn/
Dmpc8641hpcn.c75 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()

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