| /external/u-boot/arch/arm/mach-keystone/include/mach/ |
| D | clock-k2hk.h | 38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /external/u-boot/board/freescale/mx6memcal/ |
| D | Kconfig | 88 Select the type of DDR (DDR3 or LPDDR2) used on your design
90 config DDR3 config in mx6memcal specifics""choice31b0bccb0304
91 bool "DDR3"
93 Select this if your board design uses DDR3.
107 depends on DDR3
111 depends on DDR3
115 depends on DDR3
119 depends on DDR3
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| D | README | 35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
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| /external/u-boot/arch/arm/mach-mediatek/ |
| D | Kconfig | 17 including NEON and GPU, Mali-450 graphics, several DDR3 options,
29 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
39 chip and several DDR3 and DDR4 options.
48 chip and several DDR3 and DDR4 options.
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| /external/u-boot/arch/mips/mach-mscc/ |
| D | Kconfig | 65 bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
71 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
74 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3368-dmc.txt | 8 (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
19 the DDR3 device's speed-bin (as specified according to JESD-79)
51 Example (for DDR3-1600K and 800MHz)
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| /external/u-boot/board/mikrotik/crs305-1g-4s/ |
| D | README | 7 - 512 MB DDR3 RAM
22 binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI fla…
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| D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | Kconfig | 363 bool "DDR3 1333"
386 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
390 This option is the DDR3 timing used by the boot0 on H6 TV boxes
391 which use a DDR3-1333 timing.
409 Set the dram type, 3: DDR3, 7: LPDDR3
423 (for DDR3-1600) are 312 to 792.
495 Select the timings of the DDR3 chips.
503 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
505 Use the timings of the standard JEDEC DDR3-1066F speed bin for
506 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
[all …]
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| /external/u-boot/drivers/ddr/fsl/ |
| D | Kconfig | 93 Enable Freescale DDR3 controller for PowerPC SoCs.
99 Enable Freescale DDR3 controller for ARM SoCs.
131 bool "Freescale DDR3 controller"
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| /external/arm-trusted-firmware/docs/plat/marvell/ |
| D | build.rst | 107 - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB)
109 - DDR3 2CS (2): EspressoBIN V3-V5 (1GB)
111 - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB)
114 - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB
171 the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
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| /external/arm-trusted-firmware/fdts/ |
| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
19 #define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
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| D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
19 #define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
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| /external/u-boot/arch/arm/dts/ |
| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
19 #define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
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| D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
19 #define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
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| /external/u-boot/doc/device-tree-bindings/memory-controllers/ |
| D | st,stm32mp1-ddr.txt | 1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
175 st,mem-name = "DDR3 2x4Gb 533MHz";
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| /external/u-boot/arch/arm/mach-rockchip/ |
| D | Kconfig | 21 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 including NEON and GPU, Mali-400 graphics, several DDR3 options
45 including NEON and GPU, Mali-400 graphics, several DDR3 options
95 including NEON and GPU, Mali-400 graphics, several DDR3 options
126 video interfaces supporting HDMI and eDP, several DDR3 options
174 video interfaces supporting HDMI and eDP, several DDR3 options
196 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
251 video interfaces supporting HDMI and eDP, several DDR3 options
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| /external/u-boot/board/seco/mx6quq7/ |
| D | mx6quq7-2g.cfg | 76 * DDR3 SETTINGS
115 * in DDR3, 64-bit mode, only MMDC0 is init
135 /* Initialize DDR3 on CS_0 and CS_1 */
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_pctl_px30.c | 37 if (dramtype == DDR3 || dramtype == DDR4) { in pctl_write_mr()
172 if (cap_info->rank == 2 || dram_type == DDR3 || in pctl_remodify_sdram_params()
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| /external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| D | dfs.c | 110 case DDR3: in get_dram_drv_odt_val()
197 case DDR3: in sdram_timing_cfg_init()
266 if (dram_type == DDR3) { in get_rdlat_adj()
291 if (dram_type == DDR3) { in get_wrlat_adj()
421 if (timing_config->dram_type == DDR3) { in get_pi_tdfi_phy_rdlat()
493 if (timing_config->dram_type == DDR3) { in gen_rk3399_ctl_params_f0()
745 if (timing_config->dram_type == DDR3) { in gen_rk3399_ctl_params_f1()
1082 } else if (timing_config->dram_type == DDR3) { in gen_rk3399_pi_params_f0()
1099 } else if (timing_config->dram_type == DDR3) { in gen_rk3399_pi_params_f0()
1258 } else if (timing_config->dram_type == DDR3) { in gen_rk3399_pi_params_f1()
[all …]
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| /external/u-boot/board/alliedtelesis/x530/ |
| D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /external/u-boot/arch/arm/mach-mvebu/ |
| D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
|
| /external/u-boot/board/Marvell/db-xc3-24g4xg/ |
| D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | sdram.h | 11 DDR3 = 0x3, enumerator
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| /external/u-boot/board/freescale/p1_p2_rdb_pc/ |
| D | README | 13 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
17 * DDR3
|