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Searched refs:MM0 (Results 1 – 25 of 34) sorted by relevance

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/external/mesa3d/src/mesa/x86/
D3dnow_xform4.S70 MOVQ ( REGIND(EAX), MM0 ) /* x1 | x0 */
76 MOVQ ( MM0, MM2 ) /* x1 | x0 */
79 PUNPCKLDQ ( MM0, MM0 ) /* x0 | x0 */
82 MOVQ ( MM0, MM1 ) /* x0 | x0 */
85 PFMUL ( REGIND(ECX), MM0 ) /* x0*m1 | x0*m0 */
101 PFADD ( MM0, MM2 )
159 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
160 PUNPCKLDQ ( REGOFF(20, ECX), MM0 ) /* m11 | m00 */
181 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
251 MOVQ ( MM2, MM0 ) /* x1 | x0 */
[all …]
D3dnow_xform3.S70 MOVQ ( REGIND(EAX), MM0 ) /* x1 | x0 */
76 MOVQ ( MM0, MM1 ) /* x1 | x0 */
79 PUNPCKLDQ ( MM0, MM0 ) /* x0 | x0 */
85 MOVQ ( MM0, MM3 ) /* x0 | x0 */
89 PFMUL ( REGIND(ECX), MM0 ) /* x0*m1 | x0*m0 */
95 PFADD ( MM0, MM1 ) /* x0*m1+x1*m5 | x0*m0+x1*m4 */
151 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
152 PUNPCKLDQ ( REGOFF(20, ECX), MM0 ) /* m11 | m00 */
173 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
241 MOVQ ( REGIND(EAX), MM0 ) /* x1 | x0 */
[all …]
D3dnow_xform2.S63 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
64 PUNPCKLDQ ( REGOFF(16, ECX), MM0 ) /* m10 | m00 */
84 PFMUL ( MM0, MM6 ) /* x1*m10 | x0*m00 */
144 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
145 PUNPCKLDQ ( REGOFF(20, ECX), MM0 ) /* m11 | m00 */
153 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
200 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
201 PUNPCKLDQ ( REGOFF(16, ECX), MM0 ) /* m10 | m00 */
218 PFMUL ( MM0, MM6 ) /* x1*m10 | x0*m00 */
277 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
[all …]
D3dnow_xform1.S63 MOVQ ( REGIND(ECX), MM0 ) /* m01 | m00 */
76 PFMUL ( MM0, MM4 ) /* x0*m01 | x0*m00 */
131 MOVD ( REGIND(EAX), MM0 ) /* | x0 */
134 MOVD ( MM0, REGIND(EDX) ) /* | r0 */
176 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
185 PFMUL ( MM0, MM4 ) /* | x0*m00 */
234 MOVD ( REGIND(ECX), MM0 ) /* | m00 */
241 PFMUL ( MM0, MM4 ) /* 0 | x0*m00 */
288 MOVQ ( REGIND(ECX), MM0 ) /* m01 | m00 */
297 PFMUL ( MM0, MM4 ) /* x0*m01 | x0*m00 */
[all …]
Dmmx_blend.S272 PXOR ( MM0, MM0 ) /* 0x0000 | 0x0000 | 0x0000 | 0x0000 */
276 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
384 PXOR ( MM0, MM0 ) /* 0x0000 | 0x0000 | 0x0000 | 0x0000 */ ;\
392 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
/external/llvm/test/CodeGen/X86/
D2007-07-03-GR64ToVR64.ll3 ; CHECK: movd %rsi, [[MM0:%mm[0-9]+]]
5 ; CHECK: paddusw [[MM0]], [[MM1]]
Dipra-reg-usage.ll6 …R12 DR13 DR14 DR15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5…
/external/ImageMagick/PerlMagick/t/reference/write/composite/
DCopyBlue.miff41 …�MM?�MM=�MM<�MM<�MM1�MM/�MM,�MM.�MM/�MM0�MM3�MM4�MM1�MM-�MM-�MM-�MM.�MM0�MM-�MM'�MM�MM4�MMN�MM3�M…
/external/llvm/lib/Target/X86/
DX86CallingConv.td71 // MMX vector types are always returned in MM0. If the target doesn't have
72 // MM0, it doesn't support these vector types.
73 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
581 CCAssignToReg<[MM0, MM1, MM2]>>>,
DX86RegisterInfo.td152 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
DX86InstrCompiler.td456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h207 ENTRY(MM0) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h207 ENTRY(MM0) \
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h220 ENTRY(MM0) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CallingConv.td251 // MMX vector types are always returned in MM0. If the target doesn't have
252 // MM0, it doesn't support these vector types.
253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
788 CCAssignToReg<[MM0, MM1, MM2]>>>,
DX86RegisterInfo.td191 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
DX86InstrCompiler.td473 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
493 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc137 MM0 = 117,
1175 { X86::MM0 },
1812 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2322 { 41U, X86::MM0 },
2383 { 29U, X86::MM0 },
2428 { 29U, X86::MM0 },
2489 { 41U, X86::MM0 },
2550 { 29U, X86::MM0 },
2595 { 29U, X86::MM0 },
2641 { X86::MM0, 41U },
[all …]
DX86GenCallingConv.inc445 X86::MM0, X86::MM1, X86::MM2
2804 if (unsigned Reg = State.AllocateReg(X86::MM0)) {
/external/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst543 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst623 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp168 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp210 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()

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