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Searched refs:OSC (Results 1 – 25 of 43) sorted by relevance

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/external/u-boot/board/silica/pengwyn/
Dboard.c71 #define OSC (V_OSCK/1000000) macro
73 266, OSC-1, 1, -1, -1, -1, -1};
75 303, OSC-1, 1, -1, -1, -1, -1};
77 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/eets/pdu001/
Dboard.c185 #define OSC (V_OSCK / 1000000) macro
187 266, OSC - 1, 1, -1, -1, -1, -1};
189 303, OSC - 1, 1, -1, -1, -1, -1};
191 400, OSC - 1, 1, -1, -1, -1, -1};
/external/u-boot/board/birdland/bav335x/
Dboard.c175 #define OSC (V_OSCK/1000000) macro
177 266, OSC-1, 1, -1, -1, -1, -1};
179 303, OSC-1, 1, -1, -1, -1, -1};
181 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
101 CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
118 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
122 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
[all …]
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dclock.c64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
/external/u-boot/board/gumstix/pepper/
Dboard.c36 #define OSC (V_OSCK/1000000) macro
66 const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
99 const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
99 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
101 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
116 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
120 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
124 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
[all …]
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
/external/u-boot/board/vscom/baltos/
Dboard.c164 #define OSC (V_OSCK/1000000) macro
166 266, OSC-1, 1, -1, -1, -1, -1};
168 303, OSC-1, 1, -1, -1, -1, -1};
170 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dclock_am33xx.c17 #define OSC (V_OSCK/1000000) macro
62 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
64 1000, OSC-1, -1, -1, 10, 8, 4};
Dchilisom.c159 #define OSC (V_OSCK/1000000) macro
161 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/BuR/brsmarc1/
Dboard.c72 #define OSC (V_OSCK / 1000000) macro
73 const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
/external/u-boot/board/BuR/brppt1/
Dboard.c78 #define OSC (V_OSCK/1000000) macro
79 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/BuR/brxre1/
Dboard.c79 #define OSC (V_OSCK / 1000000) macro
80 const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
/external/u-boot/board/bosch/guardian/
Dboard.c70 #define OSC (V_OSCK / 1000000) macro
72 400, OSC - 1, 1, -1, -1, -1, -1};
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c61 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
63 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
65 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
66 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
67 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
68 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
/external/u-boot/board/bosch/shc/
Dboard.c279 #define OSC (V_OSCK/1000000) macro
283 #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
286 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/phytec/phycore_am335x_r2/
Dboard.c34 #define OSC (V_OSCK / 1000000) macro
36 DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
/external/u-boot/board/siemens/common/
Dboard.c102 #define OSC (V_OSCK/1000000) macro
104 DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/phytec/pcm051/
Dboard.c43 #define OSC (V_OSCK/1000000) macro
45 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/isee/igep003x/
Dboard.c142 #define OSC (V_OSCK/1000000) macro
144 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/tcl/sl50/
Dboard.c89 #define OSC (V_OSCK/1000000) macro
91 400, OSC-1, 1, -1, -1, -1, -1};
/external/u-boot/board/siemens/pxm2/
Dboard.c130 #define OSC (V_OSCK/1000000) macro
133 720, OSC-1, 1, -1, -1, -1, -1};
/external/ImageMagick/PerlMagick/t/reference/read/
Dinput_pgm_p2.miff85 …9N@<@JMF<JMJ40�jYW#=HEDHLMZT18<6DZs{=7ND:,1E1;@AAGISKNQ<FDQjeL:@A?OSC=HOK8*x_WQ;F=@EHJQ…
Dinput_pgm_p5.miff85 …9N@<@JMF<JMJ40�jYW#=HEDHLMZT18<6DZs{=7ND:,1E1;@AAGISKNQ<FDQjeL:@A?OSC=HOK8*x_WQ;F=@EHJQ…

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