| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 55 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST) in R600InstrInfo() function in R600InstrInfo
58 bool R600InstrInfo::isVector(const MachineInstr &MI) const { in isVector()
62 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
97 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, in isLegalToSplitMBBAt()
108 bool R600InstrInfo::isMov(unsigned Opcode) const { in isMov()
119 bool R600InstrInfo::isReductionOp(unsigned Opcode) const { in isReductionOp()
123 bool R600InstrInfo::isCubeOp(unsigned Opcode) const { in isCubeOp()
134 bool R600InstrInfo::isALUInstr(unsigned Opcode) const { in isALUInstr()
140 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const { in hasInstrModifiers()
148 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const { in isLDSInstr()
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| D | R600InstrInfo.h | 40 class R600InstrInfo final : public R600GenInstrInfo {
70 explicit R600InstrInfo(const R600Subtarget &);
125 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
127 R600InstrInfo::BankSwizzle TransSwz) const;
131 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
133 R600InstrInfo::BankSwizzle TransSwz) const;
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| D | R600.td | 12 def R600InstrInfo : InstrInfo {
18 let InstructionSet = R600InstrInfo;
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| D | R600MachineScheduler.h | 25 class R600InstrInfo; variable
30 const R600InstrInfo *TII = nullptr;
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| D | R600Packetizer.cpp | 58 const R600InstrInfo *TII;
229 std::vector<R600InstrInfo::BankSwizzle> &BS, in isBundlableWithCurrentPMI()
297 std::vector<R600InstrInfo::BankSwizzle> BS; in addToPacket()
328 const R600InstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | R600RegisterInfo.cpp | 36 const R600InstrInfo *TII = ST.getInstrInfo(); in getReservedRegs()
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| D | R600ISelLowering.h | 22 class R600InstrInfo; variable
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| D | AMDGPUSubtarget.h | 957 R600InstrInfo InstrInfo;
977 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
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| D | CMakeLists.txt | 86 R600InstrInfo.cpp
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| D | R600ClauseMergePass.cpp | 48 const R600InstrInfo *TII;
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| D | R600ExpandSpecialInstrs.cpp | 42 const R600InstrInfo *TII = nullptr;
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| D | R600EmitClauseMarkers.cpp | 50 const R600InstrInfo *TII = nullptr;
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| D | R600Instructions.td | 102 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
103 // and R600InstrInfo::getOperandIdx().
144 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
184 // R600InstrInfo::buildDefaultInstruction(), and
185 // R600InstrInfo::getOperandIdx().
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 31 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST) in R600InstrInfo() function in R600InstrInfo
34 bool R600InstrInfo::isTrig(const MachineInstr &MI) const { in isTrig()
38 bool R600InstrInfo::isVector(const MachineInstr &MI) const { in isVector()
42 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
77 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, in isLegalToSplitMBBAt()
88 bool R600InstrInfo::isMov(unsigned Opcode) const { in isMov()
102 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const { in isPlaceHolderOpcode()
110 bool R600InstrInfo::isReductionOp(unsigned Opcode) const { in isReductionOp()
114 bool R600InstrInfo::isCubeOp(unsigned Opcode) const { in isCubeOp()
125 bool R600InstrInfo::isALUInstr(unsigned Opcode) const { in isALUInstr()
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| D | R600InstrInfo.h | 29 class R600InstrInfo final : public AMDGPUInstrInfo {
59 explicit R600InstrInfo(const R600Subtarget &);
120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
122 R600InstrInfo::BankSwizzle TransSwz) const;
126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
128 R600InstrInfo::BankSwizzle TransSwz) const;
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| D | R600MachineScheduler.h | 24 class R600InstrInfo; variable
29 const R600InstrInfo *TII;
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| D | R600Packetizer.cpp | 60 const R600InstrInfo *TII;
231 std::vector<R600InstrInfo::BankSwizzle> &BS, in isBundlableWithCurrentPMI()
299 std::vector<R600InstrInfo::BankSwizzle> BS; in addToPacket()
330 const R600InstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | AMDGPUSubtarget.h | 296 R600InstrInfo InstrInfo;
304 const R600InstrInfo *getInstrInfo() const override { in getInstrInfo()
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| D | R600RegisterInfo.cpp | 32 const R600InstrInfo *TII = ST.getInstrInfo(); in getReservedRegs()
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| D | CMakeLists.txt | 57 R600InstrInfo.cpp
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| D | R600ISelLowering.h | 22 class R600InstrInfo; variable
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| D | R600ClauseMergePass.cpp | 48 const R600InstrInfo *TII;
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| D | R600EmitClauseMarkers.cpp | 38 const R600InstrInfo *TII;
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| D | R600Instructions.td | 91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
173 // R600InstrInfo::buildDefaultInstruction(), and
174 // R600InstrInfo::getOperandIdx().
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| D | R600ExpandSpecialInstrs.cpp | 34 const R600InstrInfo *TII;
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