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Searched refs:RegClass (Results 1 – 25 of 123) sorted by relevance

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/external/mesa3d/src/amd/compiler/
Daco_ir.h253 struct RegClass { struct
283 RegClass() = default;
284 constexpr RegClass(RC rc) in RegClass() argument
286 constexpr RegClass(RegType type, unsigned size) in RegClass() function
298 constexpr RegClass as_linear() const { return RegClass((RC) (rc | (1 << 6))); } in as_linear() argument
299 constexpr RegClass as_subdword() const { return RegClass((RC) (rc | 1 << 7)); } in as_subdword() argument
301 static constexpr RegClass get(RegType type, unsigned bytes) { in get() argument
303 return RegClass(type, DIV_ROUND_UP(bytes, 4u)); in get()
305 return bytes % 4u ? RegClass(type, bytes).as_subdword() : in get()
306 RegClass(type, bytes / 4u); in get()
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Daco_print_ir.cpp60 static void print_reg_class(const RegClass rc, FILE *output) in print_reg_class()
63 case RegClass::s1: fprintf(output, " s1: "); return; in print_reg_class()
64 case RegClass::s2: fprintf(output, " s2: "); return; in print_reg_class()
65 case RegClass::s3: fprintf(output, " s3: "); return; in print_reg_class()
66 case RegClass::s4: fprintf(output, " s4: "); return; in print_reg_class()
67 case RegClass::s6: fprintf(output, " s6: "); return; in print_reg_class()
68 case RegClass::s8: fprintf(output, " s8: "); return; in print_reg_class()
69 case RegClass::s16: fprintf(output, "s16: "); return; in print_reg_class()
70 case RegClass::v1: fprintf(output, " v1: "); return; in print_reg_class()
71 case RegClass::v2: fprintf(output, " v2: "); return; in print_reg_class()
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Daco_lower_to_hw_instr.cpp312 RegClass src0_rc = src0_reg.reg() >= 256 ? v1 : s1; in emit_int64_op()
407 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
445 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
447 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
950 RegClass def_cls = bytes % 4 == 0 ? RegClass(src.def.regClass().type(), bytes / 4u) : in split_copy()
951 RegClass(src.def.regClass().type(), bytes).as_subdword(); in split_copy()
964 RegClass op_cls = bytes % 4 == 0 ? RegClass(src.op.regClass().type(), bytes / 4u) : in split_copy()
965 RegClass(src.op.regClass().type(), bytes).as_subdword(); in split_copy()
1094 … Definition lo_half = Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
1095 … Definition dst = Definition(lo_reg, RegClass::get(RegType::vgpr, lo_half.bytes() + op.bytes())); in do_copy()
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Daco_instruction_selection_setup.cpp315 RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, unsigned bitsize) in get_reg_class()
318 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
320 return RegClass::get(type, components * bitsize / 8u); in get_reg_class()
659 RegClass *regclasses = ctx->program->temp_rc.data() + ctx->first_temp_id; in init_context()
752 …RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components, alu_instr->dest.de… in init_context()
759 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
885 …RegClass rc = get_reg_class(ctx, type, intrinsic->dest.ssa.num_components, intrinsic->dest.ssa.bit… in init_context()
934 RegClass rc = get_reg_class(ctx, type, tex->dest.ssa.num_components, in init_context()
948 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
961 regclasses[phi->dest.ssa.index] = RegClass(type, size); in init_context()
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Daco_register_allocation.cpp43 …word_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, unsigned idx, RegClass rc);
44 …bdword_operand(ra_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, unsigned byte, RegClass rc);
45 …ed> get_subdword_definition_info(Program *program, const aco_ptr<Instruction>& instr, RegClass rc);
50 RegClass rc;
53 assignment(PhysReg reg, RegClass rc) : reg(reg), rc(rc), assigned(-1) {} in assignment()
96 RegClass rc;
98 DefInfo(ra_ctx& ctx, aco_ptr<Instruction>& instr, RegClass rc_, int operand) : rc(rc_) { in DefInfo()
121 rc = RegClass::get(rc.type(), info.second); in DefInfo()
172 void block(PhysReg start, RegClass rc) { in block()
197 void clear(PhysReg start, RegClass rc) { in clear()
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Daco_reduce_assign.cpp57 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
58 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp35 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
36 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) { in constrainRegToClass()
37 unsigned NewReg = MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
57 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
66 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
67 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
69 if (!RegClass) { in constrainOperandRegClass()
85 return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass); in constrainOperandRegClass()
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DRegisterAliasing.cpp34 const llvm::MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
36 for (llvm::MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker()
77 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
79 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass)); in getRegisterClass()
/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h114 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
143 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
146 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
DRegisterClassInfo.h45 std::unique_ptr<RCInfo[]> RegClass; variable
71 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp37 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
38 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
40 RI.RegClass = nullptr; in PhysicalRegisterInfo()
43 RI.RegClass = RC; in PhysicalRegisterInfo()
67 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
172 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
233 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td563 /// RegClass - This is the register class associated with this type. For
565 RegisterClass RegClass = regclass;
658 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
668 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
675 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
676 [(set typeinfo.RegClass:$dst, EFLAGS,
677 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
684 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
685 [(set typeinfo.RegClass:$dst, EFLAGS,
686 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/InstPrinter/
DAVRInstPrinter.cpp107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
109 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td537 /// RegClass - This is the register class associated with this type. For
539 RegisterClass RegClass = regclass;
629 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
639 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
645 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
646 [(set typeinfo.RegClass:$dst, EFLAGS,
647 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
653 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
654 [(set typeinfo.RegClass:$dst, EFLAGS,
655 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DRegisterEncoder.td15 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
17 def RegOperand : RegisterOperand<RegClass> {
/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py203 for _, RegClass in RegClasses:
204 for Reg in RegClass:
208 for _, RegClass in RegClasses:
209 for Reg in RegClass:
223 for Name, RegClass in RegClasses:
226 for Reg in RegClass:
/external/v8/src/wasm/baseline/
Dliftoff-register.h22 enum RegClass : uint8_t { enum
56 static inline constexpr RegClass reg_class_for(ValueType::Kind kind) { in reg_class_for()
75 static inline constexpr RegClass reg_class_for(ValueType type) { in reg_class_for()
178 static LiftoffRegister from_code(RegClass rc, int code) { in from_code()
191 static LiftoffRegister from_external_code(RegClass rc, ValueType type, in from_external_code()
293 RegClass reg_class() const { in reg_class()
499 static constexpr LiftoffRegList GetCacheRegList(RegClass rc) { in GetCacheRegList()
/external/swiftshader/third_party/subzero/src/
DIceTypes.h36 enum RegClass : uint8_t { enum
46 static_assert(RC_Target == static_cast<RegClass>(IceType_NUM),
86 const char *regClassString(RegClass C);
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h48 std::unique_ptr<RCInfo[]> RegClass; variable
75 const RCInfo &RCI = RegClass[RC->getID()]; in get()
DRegisterScavenging.h163 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
164 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
52 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp103 const auto *RegClass = in ConvertImplicitDefToConstZero() local
105 if (RegClass == &WebAssembly::I32RegClass) { in ConvertImplicitDefToConstZero()
108 } else if (RegClass == &WebAssembly::I64RegClass) { in ConvertImplicitDefToConstZero()
111 } else if (RegClass == &WebAssembly::F32RegClass) { in ConvertImplicitDefToConstZero()
116 } else if (RegClass == &WebAssembly::F64RegClass) { in ConvertImplicitDefToConstZero()
582 const auto *RegClass = MRI.getRegClass(Reg); in MoveAndTeeForMultiUse() local
583 unsigned TeeReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse()
584 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse()
587 TII->get(GetTeeOpcode(RegClass)), TeeReg) in MoveAndTeeForMultiUse()
/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
81 RCInfo &RCI = RegClass[RC->getID()]; in compute()
DMachineRegisterInfo.cpp95 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister() argument
96 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
97 assert(RegClass->isAllocatable() && in createVirtualRegister()
103 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
93 RCInfo &RCI = RegClass[RC->getID()]; in compute()

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