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Searched refs:SEXT (Results 1 – 25 of 47) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dsignext.ll8 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
9 ; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
20 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
21 ; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
43 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 24
44 ; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 24
Dsext.ll144 ; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i16>
145 ; CHECK-NEXT: store <2 x i16> [[SEXT]], <2 x i16>* %dst, align 4
172 ; CHECK-NEXT: [[SEXT:%.*]] = add nsw i32 [[TMP1]], -1
173 ; CHECK-NEXT: ret i32 [[SEXT]]
185 ; CHECK-NEXT: [[SEXT:%.*]] = add nsw i16 [[TMP1]], -1
186 ; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
198 ; CHECK-NEXT: [[SEXT:%.*]] = ashr i32 [[TMP1]], 31
199 ; CHECK-NEXT: ret i32 [[SEXT]]
210 ; CHECK-NEXT: [[SEXT:%.*]] = ashr i16 [[TMP1]], 15
211 ; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
Dlshr.ll138 ; CHECK-NEXT: [[SEXT:%.*]] = sext i4 %x to i16
139 ; CHECK-NEXT: [[HIBIT:%.*]] = lshr i16 [[SEXT]], 12
173 ; CHECK-NEXT: [[SEXT:%.*]] = sext i3 %x to i32
174 ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[SEXT]], 31
Dselect-bitext.ll102 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48>
103 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i64> [[SEXT]], <i64 48, i64 48>
129 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16>
130 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16>
142 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %a, 16
143 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i32 [[SEXT]], 16
155 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> %a, <i32 16, i32 16>
156 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16>
Dvector-casts.ll152 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[A]], <i64 32, i64 32>
153 ; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[SEXT]], <i64 32, i64 32>
163 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> %t, <i64 32, i64 32>
164 ; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[SEXT]], <i64 32, i64 32>
Dcast.ll261 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %X, 24
262 ; CHECK-NEXT: ret i32 [[SEXT]]
648 ; CHECK-NEXT: [[SEXT:%.*]] = ashr exact i64 [[C]], 32
649 ; CHECK-NEXT: [[D:%.*]] = or i64 [[SEXT]], 1
662 ; CHECK-NEXT: [[SEXT:%.*]] = add i64 [[D]], -4294967296
663 ; CHECK-NEXT: [[E:%.*]] = ashr exact i64 [[SEXT]], 32
679 ; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[E]], 32
680 ; CHECK-NEXT: [[F:%.*]] = ashr exact i64 [[SEXT]], 32
1372 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[ICMP]] to i32
1373 ; CHECK-NEXT: ret i32 [[SEXT]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-gep.mir37 ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s8)
38 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
59 ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
60 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
Dlegalize-ext.mir371 ; X32: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
372 ; X32: $ax = COPY [[SEXT]](s16)
376 ; X64: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
377 ; X64: $ax = COPY [[SEXT]](s16)
399 ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
400 ; X32: $eax = COPY [[SEXT]](s32)
404 ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
405 ; X64: $eax = COPY [[SEXT]](s32)
427 ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
428 ; X32: $eax = COPY [[SEXT]](s32)
[all …]
Dlegalize-ext-x86-64.mir107 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
108 ; CHECK: $rax = COPY [[SEXT]](s64)
130 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
131 ; CHECK: $rax = COPY [[SEXT]](s64)
153 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
154 ; CHECK: $rax = COPY [[SEXT]](s64)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/InstrProfiling/
Dicall.ll10 …le=mips-unknown-linux -instrprof -vp-static-alloc=true -S | FileCheck %s --check-prefix=STATIC-SEXT
11 …=mips64-unknown-linux -instrprof -vp-static-alloc=true -S | FileCheck %s --check-prefix=STATIC-SEXT
42 ; STATIC-SEXT: call void @__llvm_profile_instrument_target(i64 %3, i8* bitcast ({ i64, i64, i64*, i…
46 ; STATIC-SEXT: declare void @__llvm_profile_instrument_target(i64, i8*, i32 signext)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-codegen-prepare-atp.ll50 ; CHECK: %[[SEXT:.*]] = sext i32 %i to i64
51 ; CHECK: %add = add nsw i64 %[[SEXT]], 1
52 ; CHECK: %add2 = add nsw i64 %[[SEXT]], 2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Deliminate-trunc.ll39 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[N:%.*]] to i64
44 ; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 [[IV]], [[SEXT]]
66 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[N:%.*]] to i64
71 ; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 [[IV]], [[SEXT]]
116 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[N:%.*]] to i64
121 ; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 [[IV]], [[SEXT]]
406 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[N]] to i64
411 ; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 [[IV]], [[SEXT]]
462 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[N:%.*]] to i64
467 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ne i64 [[IV]], [[SEXT]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/pseudo/
DSEXT.mir23 $r15r14 = SEXT $r31, implicit-def $sreg
DZEXT.mir23 $r15r14 = SEXT $r31, implicit-def $sreg
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dtranslate-gep.ll68 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
69 ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]]
/external/llvm/test/Transforms/InstCombine/
Dsub.ll455 ; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[ICMP]] to <2 x i32>
456 ; CHECK-NEXT: ret <2 x i32> [[SEXT]]
465 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[ICMP]] to i32
466 ; CHECK-NEXT: ret i32 [[SEXT]]
496 ; CHECK-NEXT: [[SEXT:%.*]] = sext i16 %a to i32
498 ; CHECK-NEXT: [[RET:%.*]] = sub nsw i32 [[SEXT]], [[SEXT1]]
Dcast.ll261 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %X, 24
262 ; CHECK-NEXT: ret i32 [[SEXT]]
581 ; CHECK-NEXT: [[SEXT:%.*]] = ashr exact i64 [[C]], 32
582 ; CHECK-NEXT: [[D:%.*]] = or i64 [[SEXT]], 1
595 ; CHECK-NEXT: [[SEXT:%.*]] = add i64 [[D]], -4294967296
596 ; CHECK-NEXT: [[E:%.*]] = ashr exact i64 [[SEXT]], 32
612 ; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[E]], 32
613 ; CHECK-NEXT: [[F:%.*]] = ashr exact i64 [[SEXT]], 32
1320 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[ICMP]] to i32
1321 ; CHECK-NEXT: ret i32 [[SEXT]]
Dor.ll450 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 %y to i32
451 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEXT]], %x
452 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SEXT]], [[OR]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dadd.i16.ll109 ; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
110 ; VI-NEXT: buffer_store_dword [[SEXT]]
Dsub.i16.ll111 ; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
112 ; VI-NEXT: buffer_store_dword [[SEXT]]
/external/llvm/lib/Target/AMDGPU/
DSIDefines.h94 SEXT = 1 << 0 // Integer sign-extend modifier enumerator
/external/llvm/test/CodeGen/X86/
Dcodegen-prepare-extload.ll62 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
350 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
351 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementpt…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dcodegen-prepare-extload.ll62 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
347 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
348 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementpt…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dirtranslator-amdgpu_kernel.ll54 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8)
55 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
111 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s16)
112 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
616 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s1)
617 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
635 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD1]](s1)
636 ; HSA-VI: G_STORE [[SEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIDefines.h164 SEXT = 1 << 0, // Integer sign-extend modifier enumerator

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