Home
last modified time | relevance | path

Searched refs:SRDS_PLLCR0_RFCK_SEL_125 (Results 1 – 13 of 13) sorted by relevance

/external/u-boot/board/freescale/corenet_ds/
Dcorenet_ds.c150 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; in misc_init_r()
168 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; in misc_init_r()
170 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; in misc_init_r()
172 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; in misc_init_r()
/external/u-boot/board/freescale/p2041rdb/
Dp2041rdb.c171 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, in misc_init_r()
173 SRDS_PLLCR0_RFCK_SEL_125} in misc_init_r()
/external/u-boot/arch/arm/cpu/armv7/ls102xa/
Dfsl_ls1_serdes.c125 case SRDS_PLLCR0_RFCK_SEL_125: in serdes_clock_to_string()
/external/u-boot/board/freescale/t1040qds/
Dt1040qds.c218 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; in misc_init_r()
/external/u-boot/board/keymile/kmp204x/
Dkmp204x.c184 SRDS_PLLCR0_RFCK_SEL_125}; in misc_init_r()
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dfsl_corenet_serdes.c394 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; in p4080_erratum_serdes8()
876 case SRDS_PLLCR0_RFCK_SEL_125: in serdes_clock_to_string()
Dfsl_corenet2_serdes.c386 case SRDS_PLLCR0_RFCK_SEL_125: in serdes_clock_to_string()
/external/u-boot/board/freescale/b4860qds/
Db4860qds.c1124 return SRDS_PLLCR0_RFCK_SEL_125; in serdes_refclock()
1135 ret = SRDS_PLLCR0_RFCK_SEL_125; in serdes_refclock()
/external/u-boot/arch/arm/include/asm/arch-ls102xa/
Dimmap_ls102xa.h326 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dfsl_lsch2_serdes.c90 case SRDS_PLLCR0_RFCK_SEL_125: in serdes_clock_to_string()
/external/u-boot/board/freescale/t4qds/
Dt4240qds.c657 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; in misc_init_r()
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dimmap_lsch2.h574 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h2545 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro
2629 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro