| /external/llvm/lib/Target/X86/ |
| D | X86InstrSystem.td | 19 TB;
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
51 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57 IIC_SYS_ENTER_EXIT>, TB;
60 IIC_SYS_ENTER_EXIT>, TB;
[all …]
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| D | X86InstrSVM.td | 19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
[all …]
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| D | X86InstrExtension.td | 45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
53 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
57 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
61 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
66 OpSize32, TB, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
79 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
83 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
[all …]
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| D | X86InstrVMX.td | 33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
45 "vmptrst\t$vmcs", []>, TB;
63 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
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| D | X86InstrCMovSetCC.td | 25 IIC_CMOV16_RR>, TB, OpSize16;
31 IIC_CMOV32_RR>, TB, OpSize32;
37 IIC_CMOV32_RR>, TB;
47 TB, OpSize16;
53 TB, OpSize32;
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
88 IIC_SET_R>, TB, Sched<[WriteALU]>;
92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/ADT/ |
| D | IListNodeBaseTest.cpp | 51 TrackingNode TA, TB, TC; in TEST() local
52 TA.setPrev(&TB); in TEST()
53 EXPECT_EQ(&TB, TA.getPrev()); in TEST()
55 EXPECT_EQ(nullptr, TB.getPrev()); in TEST()
56 EXPECT_EQ(nullptr, TB.getNext()); in TEST()
61 EXPECT_EQ(&TB, TA.getPrev()); in TEST()
63 EXPECT_EQ(nullptr, TB.getPrev()); in TEST()
64 EXPECT_EQ(nullptr, TB.getNext()); in TEST()
84 TrackingNode TA, TB; in TEST() local
87 TA.setPrev(&TB); in TEST()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrSystem.td | 18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
21 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
26 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
50 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
51 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
52 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
55 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
57 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
[all …]
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| D | X86InstrSVM.td | 20 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
23 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
26 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
30 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
34 def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%eax|eax}", []>, TB,
37 def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%rax|rax}", []>, TB,
42 def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%eax|eax}", []>, TB,
45 def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%rax|rax}", []>, TB,
50 def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%eax|eax}", []>, TB,
53 def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%rax|rax}", []>, TB,
[all …]
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| D | X86InstrExtension.td | 43 TB, OpSize16, Sched<[WriteALU]>;
47 TB, OpSize16, Sched<[WriteALULd]>;
51 [(set GR32:$dst, (sext GR8:$src))]>, TB,
55 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB,
59 [(set GR32:$dst, (sext GR16:$src))]>, TB,
64 OpSize32, TB, Sched<[WriteALULd]>;
69 TB, OpSize16, Sched<[WriteALU]>;
73 TB, OpSize16, Sched<[WriteALULd]>;
77 [(set GR32:$dst, (zext GR8:$src))]>, TB,
81 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB,
[all …]
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| D | X86InstrCMovSetCC.td | 26 TB, OpSize16;
32 TB, OpSize32;
37 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
46 CondNode, EFLAGS))]>, TB, OpSize16;
51 CondNode, EFLAGS))]>, TB, OpSize32;
56 CondNode, EFLAGS))]>, TB;
86 TB, Sched<[WriteSETCC]>;
90 TB, Sched<[WriteSETCCStore]>;
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| D | X86InstrSGX.td | 21 "encls", []>, TB;
25 "enclu", []>, TB;
29 "enclv", []>, TB;
|
| /external/cblas/src/ |
| D | cblas_sgemm.c | 18 char TA, TB; in cblas_sgemm() local
23 #define F77_TB &TB in cblas_sgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_sgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_sgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_sgemm()
70 F77_TB = C2F_CHAR(&TB); in cblas_sgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_sgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_sgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_sgemm()
101 F77_TB = C2F_CHAR(&TB); in cblas_sgemm()
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| D | cblas_zgemm.c | 18 char TA, TB; in cblas_zgemm() local
23 #define F77_TB &TB in cblas_zgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_zgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_zgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_zgemm()
69 F77_TB = C2F_CHAR(&TB); in cblas_zgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_zgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_zgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_zgemm()
99 F77_TB = C2F_CHAR(&TB); in cblas_zgemm()
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| D | cblas_dgemm.c | 18 char TA, TB; in cblas_dgemm() local
23 #define F77_TB &TB in cblas_dgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_dgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_dgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_dgemm()
69 F77_TB = C2F_CHAR(&TB); in cblas_dgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_dgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_dgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_dgemm()
99 F77_TB = C2F_CHAR(&TB); in cblas_dgemm()
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| D | cblas_cgemm.c | 18 char TA, TB; in cblas_cgemm() local
23 #define F77_TB &TB in cblas_cgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_cgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_cgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_cgemm()
69 F77_TB = C2F_CHAR(&TB); in cblas_cgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_cgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_cgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_cgemm()
99 F77_TB = C2F_CHAR(&TB); in cblas_cgemm()
|
| /external/tensorflow/tensorflow/core/kernels/ |
| D | sparse_tensor_dense_matmul_op_test.cc | 71 #define BM_SparseTensorDenseMatmulDev(NNZ, M, K, N, TA, TB, DEVICE) \ argument
73 BM_SparseTensorDenseMatmul##_##NNZ##_##M##_##K##_##N##_##TA##_##TB##_##DEVICE( \
75 int64 items_per_iter = (static_cast<int64>(NNZ) * (TB ? K : N)); \
79 test::Benchmark(#DEVICE, SparseTensorDenseMatmul(NNZ, M, K, N, TA, TB)) \
83 BM_SparseTensorDenseMatmul##_##NNZ##_##M##_##K##_##N##_##TA##_##TB##_##DEVICE);
85 #define BM_SparseTensorDenseMatmul(NNZ, M, K, N, TA, TB) \ argument
86 BM_SparseTensorDenseMatmulDev(NNZ, M, K, N, TA, TB, cpu); \
87 BM_SparseTensorDenseMatmulDev(NNZ, M, K, N, TA, TB, gpu);
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| D | matmul_op_test.cc | 358 #define BM_MatmulDev(M, K, N, TA, TB, T, TFTYPE, DEVICE) \ argument
359 static void BM_Matmul##_##M##_##K##_##N##_##TA##_##TB##_##TFTYPE##_##DEVICE( \
363 test::Benchmark(#DEVICE, Matmul<T>(M, K, N, TA, TB, TFTYPE)).Run(iters); \
365 BENCHMARK(BM_Matmul##_##M##_##K##_##N##_##TA##_##TB##_##TFTYPE##_##DEVICE);
369 #define BM_Matmul(M, K, N, TA, TB) \ argument
370 BM_MatmulDev(M, K, N, TA, TB, float, DT_FLOAT, cpu); \
371 BM_MatmulDev(M, K, N, TA, TB, std::complex<float>, DT_COMPLEX64, cpu); \
372 BM_MatmulDev(M, K, N, TA, TB, float, DT_FLOAT, gpu); \
373 BM_MatmulDev(M, K, N, TA, TB, std::complex<float>, DT_COMPLEX64, gpu); \
382 #define BM_Matmul(M, K, N, TA, TB) \ argument
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Other/ |
| D | lit-globbing.ll | 3 RUN: echo TB > %t/TB.txt
18 STAR-NOT: TB.txt
22 QUESTION: {{(TA.txt.*TB.txt|TB.txt.*TA.txt)}}
25 QUESTION2-NOT: TB.txt
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| /external/icu/icu4c/source/data/unit/ |
| D | mt.txt | 126 dnam{"TB"}
127 few{"{0} TB"}
128 many{"{0} TB"}
129 one{"{0} TB"}
130 other{"{0} TB"}
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| /external/clang/test/CXX/special/class.dtor/ |
| D | p3-0x.cpp | 66 struct TB { struct
67 ~TB() throw(int);
72 TB<T> b;
114 TB<T> b;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 124 FlowPattern(MachineBasicBlock *B, unsigned PR, MachineBasicBlock *TB, in FlowPattern()
126 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
247 MachineBasicBlock *TB = nullptr, *FB = nullptr; in matchFlowPattern() local
275 TB = T1B, FB = T2B; in matchFlowPattern()
277 TB = T2B, FB = T1B; in matchFlowPattern()
279 if (!MDT->properlyDominates(B, TB) || !MDT->properlyDominates(B, FB)) in matchFlowPattern()
286 unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); in matchFlowPattern()
287 unsigned TNS = TB->succ_size(), FNS = FB->succ_size(); in matchFlowPattern()
294 bool TOk = (TNP == 1 && TNS == 1 && MLI->getLoopFor(TB) == L); in matchFlowPattern()
299 if (SkipExitBranches && MLI->getLoopFor(TB) != MLI->getLoopFor(FB)) in matchFlowPattern()
[all …]
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| D | HexagonHardwareLoops.cpp | 457 MachineBasicBlock *TB = nullptr, *FB = nullptr; in findInductionRegister() local
458 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in findInductionRegister()
618 MachineBasicBlock *TB = nullptr, *FB = nullptr; in getLoopTripCount() local
619 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in getLoopTripCount()
627 assert (TB && "Exit block without a branch?"); in getLoopTripCount()
628 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in getLoopTripCount()
634 if (TB == Latch) in getLoopTripCount()
635 TB = (LTB == Header) ? LTB : LFB; in getLoopTripCount()
639 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?"); in getLoopTripCount()
640 if (!TB || (FB && TB != Header && FB != Header)) in getLoopTripCount()
[all …]
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| /external/autotest/client/site_tests/firmware_TouchMTB/ |
| D | test_conf.py | 420 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
427 GV.TB: ('vertical', 'from top to bottom',),
475 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
483 GV.TB: ('vertical', 'from top to bottom',),
508 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
517 GV.TB: ('from top to bottom',
557 variations=(GV.TB, GV.BT),
560 GV.TB: ('from top to bottom',),
721 variations=(GV.LR, GV.RL, GV.TB, GV.BT),
727 GV.TB: ('center', 'from top to bottom', 'on the right to'),
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 438 MachineBasicBlock *TB = nullptr, *FB = nullptr; in findInductionRegister() local
439 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in findInductionRegister()
585 MachineBasicBlock *TB = nullptr, *FB = nullptr; in getLoopTripCount() local
586 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in getLoopTripCount()
594 assert (TB && "Exit block without a branch?"); in getLoopTripCount()
595 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in getLoopTripCount()
601 if (TB == Latch) in getLoopTripCount()
602 TB = (LTB == Header) ? LTB : LFB; in getLoopTripCount()
606 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?"); in getLoopTripCount()
607 if (!TB || (FB && TB != Header && FB != Header)) in getLoopTripCount()
[all …]
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| D | HexagonEarlyIfConv.cpp | 107 FlowPattern(MachineBasicBlock *B, unsigned PR, MachineBasicBlock *TB, in FlowPattern()
109 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
220 MachineBasicBlock *TB = 0, *FB = 0; in matchFlowPattern() local
251 TB = T1B, FB = T2B; in matchFlowPattern()
253 TB = T2B, FB = T1B; in matchFlowPattern()
255 if (!MDT->properlyDominates(B, TB) || !MDT->properlyDominates(B, FB)) in matchFlowPattern()
262 unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); in matchFlowPattern()
263 unsigned TNS = TB->succ_size(), FNS = FB->succ_size(); in matchFlowPattern()
276 MachineBasicBlock *TSB = (TNS > 0) ? *TB->succ_begin() : 0; in matchFlowPattern()
294 if (FSB == TB) { in matchFlowPattern()
[all …]
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