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Searched refs:UseMI (Results 1 – 25 of 101) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp92 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
96 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
187 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode(); in canRemoveAddasl() local
191 MI.getParent() != UseMI.getParent()) in canRemoveAddasl()
194 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
196 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset || in canRemoveAddasl()
197 getBaseWithLongOffset(UseMI) < 0) in canRemoveAddasl()
201 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() && in canRemoveAddasl()
202 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg()) in canRemoveAddasl()
205 for (auto &Mo : UseMI.operands()) in canRemoveAddasl()
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/external/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp78 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
165 MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode(); in canRemoveAddasl() local
169 MI->getParent() != UseMI->getParent()) in canRemoveAddasl()
172 const MCInstrDesc &UseMID = UseMI->getDesc(); in canRemoveAddasl()
174 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset || in canRemoveAddasl()
175 getBaseWithLongOffset(UseMI) < 0) in canRemoveAddasl()
179 if (UseMID.mayStore() && UseMI->getOperand(2).isReg() && in canRemoveAddasl()
180 UseMI->getOperand(2).getReg() == MI->getOperand(0).getReg()) in canRemoveAddasl()
183 for (auto &Mo : UseMI->operands()) in canRemoveAddasl()
441 MachineInstr *UseMI = UseIA.Addr->getCode(); in changeAddAsl() local
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/external/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp50 MachineInstr *UseMI; member
56 UseMI(MI), UseOpNo(OpNo) { in FoldCandidate()
101 MachineInstr *MI = Fold.UseMI; in updateOperand()
125 if (Candidate.UseMI == MI) in isUseMIInFoldList()
191 static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI, in foldOperand() argument
197 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in foldOperand()
236 if (UseMI->getOpcode() == AMDGPU::COPY) { in foldOperand()
237 unsigned DestReg = UseMI->getOperand(0).getReg(); in foldOperand()
247 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
248 CopiesToReplace.push_back(UseMI); in foldOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp32 MachineInstr *UseMI; member
44 UseMI(MI), OpToFold(nullptr), UseOpNo(OpNo), Kind(FoldOp->getType()), in FoldCandidate()
82 MachineInstr *UseMI,
122 const MachineInstr &UseMI, in isInlineConstantIfFolded() argument
125 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) in isInlineConstantIfFolded()
128 unsigned Opc = UseMI.getOpcode(); in isInlineConstantIfFolded()
158 MachineInstr *MI = Fold.UseMI; in updateOperand()
218 if (Candidate.UseMI == MI) in isUseMIInFoldList()
313 MachineInstr *UseMI, in foldOperand() argument
317 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in foldOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineTraceMetrics.cpp652 static bool getDataDeps(const MachineInstr &UseMI, in getDataDeps() argument
656 if (UseMI.isDebugInstr()) in getDataDeps()
660 for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(), in getDataDeps()
661 E = UseMI.operands_end(); I != E; ++I) { in getDataDeps()
674 Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I))); in getDataDeps()
682 static void getPHIDeps(const MachineInstr &UseMI, in getPHIDeps() argument
689 assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI"); in getPHIDeps()
690 for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) { in getPHIDeps()
691 if (UseMI.getOperand(i + 1).getMBB() == Pred) { in getPHIDeps()
692 unsigned Reg = UseMI.getOperand(i).getReg(); in getPHIDeps()
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DLiveRangeEdit.cpp188 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
200 if (UseMI && UseMI != MI) in foldAsLoad()
205 UseMI = MI; in foldAsLoad()
208 if (!DefMI || !UseMI) in foldAsLoad()
214 LIS.getInstructionIndex(*UseMI))) in foldAsLoad()
224 << " into single use: " << *UseMI); in foldAsLoad()
227 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) in foldAsLoad()
230 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS); in foldAsLoad()
234 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); in foldAsLoad()
235 UseMI->eraseFromParent(); in foldAsLoad()
DTargetSchedule.cpp187 const MachineInstr *UseMI, unsigned UseOperIdx) const { in computeOperandLatency() argument
194 if (UseMI) { in computeOperandLatency()
196 *UseMI, UseOperIdx); in computeOperandLatency()
226 if (!UseMI) in computeOperandLatency()
230 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
233 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency()
DRegisterScavenging.cpp310 MachineBasicBlock::iterator &UseMI) { in findSurvivorReg() argument
367 UseMI = RestorePointMI; in findSurvivorReg()
463 MachineBasicBlock::iterator &UseMI) { in spill() argument
508 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) { in spill()
525 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex, in spill()
527 II = std::prev(UseMI); in spill()
559 MachineBasicBlock::iterator UseMI; in scavengeRegister() local
560 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister()
568 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); in scavengeRegister()
569 Scavenged.Restore = &*std::prev(UseMI); in scavengeRegister()
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DMachineLICM.cpp969 for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) { in isCopyFeedingInvariantStore()
970 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI)) in isCopyFeedingInvariantStore()
1066 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in HasLoopPHIUse()
1068 if (UseMI.isPHI()) { in HasLoopPHIUse()
1071 if (CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1076 if (isExitBlock(UseMI.getParent())) in HasLoopPHIUse()
1081 if (UseMI.isCopy() && CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1082 Work.push_back(&UseMI); in HasLoopPHIUse()
1097 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in HasHighOperandLatency()
1098 if (UseMI.isCopyLike()) in HasHighOperandLatency()
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DDetectDeadLanes.cpp424 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes() local
425 if (UseMI.isKill()) in determineInitialUsedLanes()
429 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
430 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
431 const MachineOperand &Def = *UseMI.defs().begin(); in determineInitialUsedLanes()
438 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
440 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
442 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); in determineInitialUsedLanes()
DOptimizePHIs.cpp156 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
157 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) in IsDeadPHICycle()
DMachineSSAUpdater.cpp225 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
227 if (UseMI->isPHI()) { in RewriteUse()
228 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U); in RewriteUse()
231 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
DRegisterCoalescer.cpp753 MachineInstr *UseMI = MO.getParent(); in removeCopyByCommutingDef() local
754 unsigned OpNo = &MO - &UseMI->getOperand(0); in removeCopyByCommutingDef()
755 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef()
760 if (UseMI->isRegTiedToDefOperand(OpNo)) in removeCopyByCommutingDef()
802 MachineInstr *UseMI = UseMO.getParent(); in removeCopyByCommutingDef() local
803 if (UseMI->isDebugValue()) { in removeCopyByCommutingDef()
809 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef()
820 if (UseMI == CopyMI) in removeCopyByCommutingDef()
822 if (!UseMI->isCopy()) in removeCopyByCommutingDef()
824 if (UseMI->getOperand(0).getReg() != IntB.reg || in removeCopyByCommutingDef()
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/external/llvm/lib/CodeGen/
DMachineTraceMetrics.cpp628 static bool getDataDeps(const MachineInstr &UseMI, in getDataDeps() argument
632 if (UseMI.isDebugValue()) in getDataDeps()
636 for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(), in getDataDeps()
637 E = UseMI.operands_end(); I != E; ++I) { in getDataDeps()
650 Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I))); in getDataDeps()
658 static void getPHIDeps(const MachineInstr &UseMI, in getPHIDeps() argument
665 assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI"); in getPHIDeps()
666 for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) { in getPHIDeps()
667 if (UseMI.getOperand(i + 1).getMBB() == Pred) { in getPHIDeps()
668 unsigned Reg = UseMI.getOperand(i).getReg(); in getPHIDeps()
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DLiveRangeEdit.cpp166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
178 if (UseMI && UseMI != MI) in foldAsLoad()
183 UseMI = MI; in foldAsLoad()
186 if (!DefMI || !UseMI) in foldAsLoad()
192 LIS.getInstructionIndex(*UseMI))) in foldAsLoad()
202 << " into single use: " << *UseMI); in foldAsLoad()
205 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) in foldAsLoad()
208 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS); in foldAsLoad()
212 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); in foldAsLoad()
213 UseMI->eraseFromParent(); in foldAsLoad()
DTargetSchedule.cpp156 const MachineInstr *UseMI, unsigned UseOperIdx) const { in computeOperandLatency() argument
163 if (UseMI) { in computeOperandLatency()
165 *UseMI, UseOperIdx); in computeOperandLatency()
195 if (!UseMI) in computeOperandLatency()
199 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency()
DRegisterScavenging.cpp279 MachineBasicBlock::iterator &UseMI) { in findSurvivorReg() argument
336 UseMI = RestorePointMI; in findSurvivorReg()
372 MachineBasicBlock::iterator UseMI; in scavengeRegister() local
373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister()
424 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
441 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex, in scavengeRegister()
443 II = std::prev(UseMI); in scavengeRegister()
449 Scavenged[SI].Restore = &*std::prev(UseMI); in scavengeRegister()
DDetectDeadLanes.cpp426 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes() local
427 if (UseMI.isKill()) in determineInitialUsedLanes()
431 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
432 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
433 const MachineOperand &Def = *UseMI.defs().begin(); in determineInitialUsedLanes()
440 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
442 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
444 DEBUG(dbgs() << "Copy accross incompatible classes: " << UseMI); in determineInitialUsedLanes()
DOptimizePHIs.cpp147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { in IsDeadPHICycle()
148 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) in IsDeadPHICycle()
DMachineLICM.cpp942 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in HasLoopPHIUse()
944 if (UseMI.isPHI()) { in HasLoopPHIUse()
947 if (CurLoop->contains(&UseMI)) in HasLoopPHIUse()
952 if (isExitBlock(UseMI.getParent())) in HasLoopPHIUse()
957 if (UseMI.isCopy() && CurLoop->contains(&UseMI)) in HasLoopPHIUse()
958 Work.push_back(&UseMI); in HasLoopPHIUse()
972 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in HasHighOperandLatency()
973 if (UseMI.isCopyLike()) in HasHighOperandLatency()
975 if (!CurLoop->contains(UseMI.getParent())) in HasHighOperandLatency()
977 for (unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) { in HasHighOperandLatency()
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DRegisterCoalescer.cpp703 MachineInstr *UseMI = MO.getParent(); in removeCopyByCommutingDef() local
704 unsigned OpNo = &MO - &UseMI->getOperand(0); in removeCopyByCommutingDef()
705 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef()
710 if (UseMI->isRegTiedToDefOperand(OpNo)) in removeCopyByCommutingDef()
752 MachineInstr *UseMI = UseMO.getParent(); in removeCopyByCommutingDef() local
753 if (UseMI->isDebugValue()) { in removeCopyByCommutingDef()
759 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef()
770 if (UseMI == CopyMI) in removeCopyByCommutingDef()
772 if (!UseMI->isCopy()) in removeCopyByCommutingDef()
774 if (UseMI->getOperand(0).getReg() != IntB.reg || in removeCopyByCommutingDef()
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DMachineSSAUpdater.cpp222 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
224 if (UseMI->isPHI()) { in RewriteUse()
225 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U); in RewriteUse()
228 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg() local
125 if (UseMI->getParent() != MBB) in getDefReg()
128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
129 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
134 if (UseMI->getParent() != MBB) in getDefReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg() local
125 if (UseMI->getParent() != MBB) in getDefReg()
128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
129 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
134 if (UseMI->getParent() != MBB) in getDefReg()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp143 const MachineInstr &UseMI, in getOperandLatency() argument
146 UseMI, UseIdx); in getOperandLatency()
165 if (UseMI.isBranch() && IsRegCR) { in getOperandLatency()
1213 bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
1229 const MCInstrDesc &UseMCID = UseMI.getDesc(); in FoldImmediate()
1236 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) in FoldImmediate()
1237 if (UseMI.getOperand(UseIdx).isReg() && in FoldImmediate()
1238 UseMI.getOperand(UseIdx).getReg() == Reg) in FoldImmediate()
1241 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); in FoldImmediate()
1273 UseMI.getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
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