Searched refs:ddr_regs (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/arch/mips/mach-ath79/ar934x/ |
| D | ddr.c | 39 void __iomem *ddr_regs; in ar934x_ddr_init() local
44 ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in ar934x_ddr_init()
66 writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG); in ar934x_ddr_init()
69 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
72 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
75 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); in ar934x_ddr_init()
82 writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF); in ar934x_ddr_init()
86 writel(0x13b, ddr_regs + 0x118); in ar934x_ddr_init()
92 writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG); in ar934x_ddr_init()
95 writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); in ar934x_ddr_init()
[all …]
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| /external/u-boot/arch/mips/mach-ath79/qca956x/ |
| D | ddr.c | 190 void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in qca956x_ddr_init() local
205 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); in qca956x_ddr_init()
208 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); in qca956x_ddr_init()
211 writel(ctl_config, ddr_regs + QCA956X_DDR_REG_CTL_CONF); in qca956x_ddr_init()
214 writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in qca956x_ddr_init()
217 writel(0x74444444, ddr_regs + QCA956X_DDR_REG_BURST); in qca956x_ddr_init()
220 writel(0x44444444, ddr_regs + QCA956X_DDR_REG_BURST2); in qca956x_ddr_init()
223 writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL); in qca956x_ddr_init()
226 writel(0xfffff, ddr_regs + QCA956X_DDR_REG_TIMEOUT_MAX); in qca956x_ddr_init()
229 writel(ddr_config, ddr_regs + AR71XX_DDR_REG_CONFIG); in qca956x_ddr_init()
[all …]
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| /external/u-boot/arch/arm/cpu/arm926ejs/armada100/ |
| D | dram.c | 39 struct armd1ddr_registers *ddr_regs = in armd1_sdram_base() local
42 u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); in armd1_sdram_base()
47 result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; in armd1_sdram_base()
56 struct armd1ddr_registers *ddr_regs = in armd1_sdram_size() local
59 u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); in armd1_sdram_size()
64 result = readl(&ddr_regs->mmap[chip_sel].cs); in armd1_sdram_size()
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| /external/u-boot/arch/arm/include/asm/arch-am33xx/ |
| D | ddr_defs.h | 252 struct ddr_regs { struct
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