Searched refs:dramtmg0 (Results 1 – 17 of 17) sorted by relevance
92 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; in cl_som_imx7_spl_dram_cfg_size()103 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; in cl_som_imx7_spl_dram_cfg_size()114 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; in cl_som_imx7_spl_dram_cfg_size()125 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A; in cl_som_imx7_spl_dram_cfg_size()
41 .dramtmg0 = 0x09081109,58 .dramtmg0 = 0x09081109,
53 writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0); in mx7_dram_cfg()
28 u32 dramtmg0; /* 0x0100 */ member
67 uint32_t dramtmg0; member
49 uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */ member
71 u32 dramtmg0; member
46 u32 dramtmg0; /* 0x100 SDRAM Timing 0*/ member
100 DDRCTL_REG_TIMING(dramtmg0),
84 u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ member
120 u32 dramtmg0; /* 0x100 */ member
139 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
158 &mctl_ctl->dramtmg0); in mctl_init()
171 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
34 u32 dramtmg0; member131 u32 dramtmg0; member
80 DDRCTL_REG_TIMING(dramtmg0),