| /external/arm-trusted-firmware/drivers/arm/gic/v2/ |
| D | gicv2_main.c | 81 assert(driver_data->gicd_base != 0U); in gicv2_pcpu_distif_init()
83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, in gicv2_pcpu_distif_init()
88 ctlr = gicd_read_ctlr(driver_data->gicd_base); in gicv2_pcpu_distif_init()
90 gicd_write_ctlr(driver_data->gicd_base, in gicv2_pcpu_distif_init()
105 assert(driver_data->gicd_base != 0U); in gicv2_distif_init()
108 ctlr = gicd_read_ctlr(driver_data->gicd_base); in gicv2_distif_init()
109 gicd_write_ctlr(driver_data->gicd_base, in gicv2_distif_init()
113 gicv2_spis_configure_defaults(driver_data->gicd_base); in gicv2_distif_init()
115 gicv2_secure_spis_configure_props(driver_data->gicd_base, in gicv2_distif_init()
121 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); in gicv2_distif_init()
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| D | gicv2_helpers.c | 93 void gicv2_spis_configure_defaults(uintptr_t gicd_base) in gicv2_spis_configure_defaults() argument
97 num_ints = gicd_read_typer(gicd_base); in gicv2_spis_configure_defaults()
106 gicd_write_igroupr(gicd_base, index, ~0U); in gicv2_spis_configure_defaults()
110 gicd_write_ipriorityr(gicd_base, in gicv2_spis_configure_defaults()
116 gicd_write_icfgr(gicd_base, index, 0U); in gicv2_spis_configure_defaults()
122 void gicv2_secure_spis_configure_props(uintptr_t gicd_base, in gicv2_secure_spis_configure_props() argument
141 gicd_clr_igroupr(gicd_base, prop_desc->intr_num); in gicv2_secure_spis_configure_props()
144 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
148 gicd_set_itargetsr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
149 gicv2_get_cpuif_id(gicd_base)); in gicv2_secure_spis_configure_props()
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| D | gicv2_private.h | 18 void gicv2_spis_configure_defaults(uintptr_t gicd_base);
19 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
22 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
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| /external/arm-trusted-firmware/drivers/arm/gic/v3/ |
| D | gicv3_main.c | 65 assert(plat_driver_data->gicd_base != 0U); in gicv3_driver_init()
84 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); in gicv3_driver_init()
93 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); in gicv3_driver_init()
148 assert(gicv3_driver_data->gicd_base != 0U); in gicv3_distif_init()
157 gicd_clr_ctlr(gicv3_driver_data->gicd_base, in gicv3_distif_init()
164 gicd_set_ctlr(gicv3_driver_data->gicd_base, in gicv3_distif_init()
168 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); in gicv3_distif_init()
171 gicv3_driver_data->gicd_base, in gicv3_distif_init()
176 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); in gicv3_distif_init()
193 assert(gicv3_driver_data->gicd_base != 0U); in gicv3_rdistif_init()
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| D | gicv3_helpers.c | 355 void gicv3_spis_config_defaults(uintptr_t gicd_base) in gicv3_spis_config_defaults() argument
359 num_ints = gicd_read_typer(gicd_base); in gicv3_spis_config_defaults()
368 gicd_write_igroupr(gicd_base, index, ~0U); in gicv3_spis_config_defaults()
372 gicd_write_ipriorityr(gicd_base, in gicv3_spis_config_defaults()
381 gicd_write_icfgr(gicd_base, index, 0U); in gicv3_spis_config_defaults()
387 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, in gicv3_secure_spis_config_props() argument
407 gicd_clr_igroupr(gicd_base, current_prop->intr_num); in gicv3_secure_spis_config_props()
413 gicd_set_igrpmodr(gicd_base, current_prop->intr_num); in gicv3_secure_spis_config_props()
416 gicd_clr_igrpmodr(gicd_base, current_prop->intr_num); in gicv3_secure_spis_config_props()
421 gicd_set_icfgr(gicd_base, current_prop->intr_num, in gicv3_secure_spis_config_props()
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| D | gicv3_private.h | 98 void gicv3_spis_config_defaults(uintptr_t gicd_base);
103 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
122 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) in gicd_wait_for_pending_write() argument
124 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) in gicd_wait_for_pending_write()
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| /external/arm-trusted-firmware/plat/layerscape/common/tsp/ |
| D | ls_tsp_setup.c | 22 .gicd_base = GICD_BASE,
48 uint32_t gicc_base, gicd_base; in tsp_platform_setup() local
51 get_gic_offset(&gicc_base, &gicd_base); in tsp_platform_setup()
52 ls_gic_data.gicd_base = (uintptr_t)gicd_base; in tsp_platform_setup()
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| /external/arm-trusted-firmware/plat/layerscape/board/ls1043/ |
| D | ls_gic.c | 23 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) in get_gic_offset() argument
40 *gicd_base = GICD_BASE; in get_gic_offset()
43 *gicd_base = GICD_BASE_64K; in get_gic_offset()
47 *gicd_base = GICD_BASE; in get_gic_offset()
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_bl31_setup.c | 32 .gicd_base = GICD_BASE,
151 uint32_t gicc_base, gicd_base; in ls_bl31_platform_setup() local
155 get_gic_offset(&gicc_base, &gicd_base); in ls_bl31_platform_setup()
156 ls_gic_data.gicd_base = (uintptr_t)gicd_base; in ls_bl31_platform_setup()
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| /external/arm-trusted-firmware/plat/ti/k3/common/ |
| D | k3_gicv3.c | 43 uintptr_t gicd_base = gic_base; in k3_gic_driver_init() local
65 k3_gic_data.gicd_base = gicd_base; in k3_gic_driver_init()
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| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_gicv3.c | 61 .gicd_base = 0x5fe00000,
70 .gicd_base = 0x5fe00000,
79 .gicd_base = 0x5fe00000,
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| /external/arm-trusted-firmware/plat/layerscape/common/include/ |
| D | soc.h | 16 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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| /external/arm-trusted-firmware/plat/imx/imx8m/ |
| D | gpc_common.c | 172 uintptr_t gicd_base = PLAT_GICD_BASE; in imx_set_sys_wakeup() local
185 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); in imx_set_sys_wakeup()
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| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | qemu_gicv2.c | 17 .gicd_base = GICD_BASE,
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| D | qemu_gicv3.c | 25 .gicd_base = GICD_BASE,
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| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_gicv2.c | 32 tegra_gic_data.gicd_base = TEGRA_GICD_BASE; in tegra_gic_setup()
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/ |
| D | plat_mt_gic.c | 19 .gicd_base = BASE_GICD_BASE,
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| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | rockchip_gicv2.c | 37 .gicd_base = PLAT_RK_GICD_BASE,
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| D | rockchip_gicv3.c | 39 .gicd_base = PLAT_RK_GICD_BASE,
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| /external/arm-trusted-firmware/plat/hisilicon/poplar/ |
| D | poplar_gicv2.c | 24 .gicd_base = POPLAR_GICD_BASE,
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| /external/arm-trusted-firmware/plat/arm/common/ |
| D | arm_gicv2.c | 35 .gicd_base = PLAT_ARM_GICD_BASE,
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| /external/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_gicv3.c | 60 .gicd_base = PLAT_SQ_GICD_BASE,
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| /external/arm-trusted-firmware/plat/marvell/common/ |
| D | marvell_gicv3.c | 65 .gicd_base = PLAT_MARVELL_GICD_BASE,
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| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | versal_gicv3.c | 63 .gicd_base = PLAT_VERSAL_GICD_BASE,
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| /external/arm-trusted-firmware/plat/imx/common/ |
| D | plat_imx8_gic.c | 33 .gicd_base = PLAT_GICD_BASE,
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