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Searched refs:isAllocatable (Results 1 – 25 of 66) sorted by relevance

123

/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp112 if (!RC || RC->isAllocatable()) in getAllocatableClass()
118 if (SubRC->isAllocatable()) in getAllocatableClass()
149 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
166 if ((*I)->isAllocatable()) in getAllocatableSet()
DMachineRegisterInfo.cpp40 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
97 assert(RegClass->isAllocatable() && in createVirtualRegister()
455 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
DRegAllocFast.cpp536 !RC->contains(Hint) || !MRI->isAllocatable(Hint))) in allocVirtReg()
814 if (MRI->isAllocatable(LI.PhysReg)) in AllocateBasicBlock()
953 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
1040 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
DCalcSpillWeights.cpp194 if (hweight > bestPhys && mri.isAllocatable(hint)) { in calculateSpillWeightAndHint()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td155 let isAllocatable = 0;
160 let isAllocatable = 0;
218 let isAllocatable = 0;
403 let isAllocatable = 0;
409 let isAllocatable = 0;
444 let isAllocatable = 0;
467 let isAllocatable = 0;
482 let isAllocatable = 0;
497 let isAllocatable = 0;
550 let isAllocatable = 0;
[all …]
DR600RegisterInfo.td160 let isAllocatable = 0 in {
206 } // End isAllocatable = 0
DSIFrameLowering.cpp138 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) { in getReservedPrivateSegmentBufferReg()
204 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) { in getReservedPrivateSegmentWaveByteOffsetReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp175 if (!RC || RC->isAllocatable()) in getAllocatableClass()
181 if (SubRC->isAllocatable()) in getAllocatableClass()
211 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
227 if (C->isAllocatable()) in getAllocatableSet()
DMachineRegisterInfo.cpp60 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
169 assert(RegClass->isAllocatable() && in createVirtualRegister()
525 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
DRegAllocFast.cpp555 MRI->isAllocatable(Hint) && RC.contains(Hint)) { in allocVirtReg()
864 if (MRI->isAllocatable(LI.PhysReg)) in allocateBasicBlock()
963 if (!MRI->isAllocatable(Reg)) continue; in allocateBasicBlock()
1045 if (!MRI->isAllocatable(Reg)) continue; in allocateBasicBlock()
DCalcSpillWeights.cpp277 if (TargetRegisterInfo::isVirtualRegister(hint) || mri.isAllocatable(hint)) in weightCalcHelper()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td346 let Size = 32, isAllocatable = 0 in
353 let isAllocatable = 0 in
356 let Size = 64, isAllocatable = 0 in
361 let Size = 32, isAllocatable = 0 in
371 let Size = 64, isAllocatable = 0 in
382 let isAllocatable = 0 in
388 let Size = 32, isAllocatable = 0 in
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td120 let isAllocatable = 0;
177 let isAllocatable = 0;
275 let isAllocatable = 0;
291 let isAllocatable = 0;
DSIFrameLowering.cpp165 assert(MRI.isAllocatable(Reg)); in emitPrologue()
195 if (!MRI.isAllocatable(Reg) || in emitPrologue()
DR600RegisterInfo.td159 let isAllocatable = 0 in {
205 } // End isAllocatable = 0
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td58 let isAllocatable = 0;
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td58 let isAllocatable = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td63 let isAllocatable = 0;
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td63 let isAllocatable = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td389 let isAllocatable = 0 in
398 let isAllocatable = 0 in
522 let isAllocatable = 0;
547 let isAllocatable = 0;
551 let isAllocatable = 0;
555 let isAllocatable = 0;
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h120 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h106 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp66 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td257 let Size = 32, isAllocatable = 0 in
264 let Size = 64, isAllocatable = 0 in
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td45 let isAllocatable = allocatable in
299 let isAllocatable = 0, CopyCost = -1 in

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