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Searched refs:lane2 (Results 1 – 15 of 15) sorted by relevance

/external/tensorflow/third_party/eigen3/unsupported/Eigen/CXX11/src/FixedPoint/
DPacketMathAVX512.h427 Packet4i lane2 = _mm512_extracti32x4_epi32(a.val, 2);
430 _mm_min_epi32(_mm_min_epi32(lane0, lane1), _mm_min_epi32(lane2, lane3));
439 Packet4i lane2 = _mm512_extracti32x4_epi32(a.val, 2);
442 _mm_max_epi32(_mm_max_epi32(lane0, lane1), _mm_max_epi32(lane2, lane3));
451 Packet4i lane2 = _mm512_extracti32x4_epi32(a.val, 2);
454 _mm_min_epi16(_mm_min_epi16(lane0, lane1), _mm_min_epi16(lane2, lane3));
465 Packet4i lane2 = _mm512_extracti32x4_epi32(a.val, 2);
468 _mm_max_epi16(_mm_max_epi16(lane0, lane1), _mm_max_epi16(lane2, lane3));
479 Packet4i lane2 = _mm512_extracti32x4_epi32(a.val, 2);
482 _mm_min_epu8(_mm_min_epu8(lane0, lane1), _mm_min_epu8(lane2, lane3));
[all …]
/external/eigen/Eigen/src/Core/arch/AVX512/
DPacketMath.h890 Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);
892 Packet4f sum = padd(padd(lane0, lane1), padd(lane2, lane3));
916 Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);
918 Packet4f sum0 = padd(lane0, lane2);
944 Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);
946 Packet4f res = pmul(pmul(lane0, lane1), pmul(lane2, lane3));
964 Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);
966 Packet4f res = _mm_min_ps(_mm_min_ps(lane0, lane1), _mm_min_ps(lane2, lane3));
983 Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);
985 Packet4f res = _mm_max_ps(_mm_max_ps(lane0, lane1), _mm_max_ps(lane2, lane3));
/external/mesa3d/prebuilt-intermediates/bifrost/
Dbi_generated_pack.h48 unsigned lane2 = lane2_temp; in pan_pack_fma_rshift_and_i32() local
49 assert(lane2 < 4); in pan_pack_fma_rshift_and_i32()
57 …return 0x301000 | (src0 << 0) | (src1 << 3) | (src2 << 6) | (lane2 << 9) | (not1 << 14) | (not_res… in pan_pack_fma_rshift_and_i32()
256 unsigned lane2 = lane2_temp; in pan_pack_fma_rrot_double_i32() local
257 assert(lane2 < 2); in pan_pack_fma_rrot_double_i32()
261 …return 0x33a000 | (src0 << 0) | (src1 << 3) | (src2 << 6) | (bytes2 << 9) | (lane2 << 10) | (resul… in pan_pack_fma_rrot_double_i32()
773 unsigned lane2 = lane2_temp; in pan_pack_fma_arshift_double_i32() local
774 assert(lane2 < 2); in pan_pack_fma_arshift_double_i32()
778 …return 0x33e000 | (src0 << 0) | (src1 << 3) | (src2 << 6) | (bytes2 << 9) | (lane2 << 10) | (resul… in pan_pack_fma_arshift_double_i32()
2491 unsigned lane2 = lane2_temp; in pan_pack_fma_lshift_double_i32() local
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Dbifrost_gen_disasm.c1311 const char *lane2 = lane2_table[_BITS(bits, 14, 1)]; in bi_disasm_fma_mkvec_v4i8() local
1332 fputs(lane2, fp); in bi_disasm_fma_mkvec_v4i8()
1636 const char *lane2 = lane2_table[_BITS(bits, 10, 1)]; in bi_disasm_fma_rrot_double_i32() local
1657 fputs(lane2, fp); in bi_disasm_fma_rrot_double_i32()
1860 const char *lane2 = lane2_table[_BITS(bits, 9, 2)]; in bi_disasm_fma_rshift_or_i32() local
1887 fputs(lane2, fp); in bi_disasm_fma_rshift_or_i32()
1966 const char *lane2 = lane2_table[_BITS(bits, 10, 1)]; in bi_disasm_fma_lshift_double_i32() local
1987 fputs(lane2, fp); in bi_disasm_fma_lshift_double_i32()
3225 const char *lane2 = lane2_table[_BITS(bits, 9, 2)]; in bi_disasm_fma_lshift_xor_i32() local
3245 fputs(lane2, fp); in bi_disasm_fma_lshift_xor_i32()
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/external/u-boot/arch/arm/dts/
Dzynqmp-zcu104-revA.dts280 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
Dzynqmp-zcu104-revC.dts293 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
Dzynqmp-zcu100-revC.dts321 phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;
Dzynqmp.dtsi762 lane2: lane2 { label
Dzynqmp-zcu216-revA.dts591 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
Dzynqmp-zcu111-revA.dts592 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
Dzynqmp-zcu106-revA.dts682 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
Dzynqmp-zcu102-revA.dts684 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
/external/mesa3d/src/amd/llvm/
Dac_llvm_build.h533 unsigned lane1, unsigned lane2, unsigned lane3);
Dac_llvm_build.c3416 static inline enum dpp_ctrl dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, in dpp_quad_perm() argument
3419 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); in dpp_quad_perm()
3420 return _dpp_quad_perm | lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6); in dpp_quad_perm()
4262 unsigned lane1, unsigned lane2, unsigned lane3) in ac_build_quad_swizzle() argument
4264 unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3); in ac_build_quad_swizzle()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-2velem.ll2795 %lane2 = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
2796 %1 = fmul <4 x float> %lane2, %c
2814 %lane2 = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
2815 %1 = fmul <4 x float> %lane2, %c