| /external/cpuinfo/src/arm/ |
| D | midr.h | 39 inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) { in midr_set_implementer() argument
40 return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) | in midr_set_implementer()
44 inline static uint32_t midr_set_variant(uint32_t midr, uint32_t variant) { in midr_set_variant() argument
45 return (midr & ~CPUINFO_ARM_MIDR_VARIANT_MASK) | in midr_set_variant()
49 inline static uint32_t midr_set_architecture(uint32_t midr, uint32_t architecture) { in midr_set_architecture() argument
50 return (midr & ~CPUINFO_ARM_MIDR_ARCHITECTURE_MASK) | in midr_set_architecture()
54 inline static uint32_t midr_set_part(uint32_t midr, uint32_t part) { in midr_set_part() argument
55 return (midr & ~CPUINFO_ARM_MIDR_PART_MASK) | in midr_set_part()
59 inline static uint32_t midr_set_revision(uint32_t midr, uint32_t revision) { in midr_set_revision() argument
60 return (midr & ~CPUINFO_ARM_MIDR_REVISION_MASK) | in midr_set_revision()
[all …]
|
| D | uarch.c | 9 uint32_t midr, in cpuinfo_arm_decode_vendor_uarch() argument
16 switch (midr_get_implementer(midr)) { in cpuinfo_arm_decode_vendor_uarch()
19 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
98 switch (midr_get_part(midr) >> 8) { in cpuinfo_arm_decode_vendor_uarch()
111 cpuinfo_log_warning("unknown ARM CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); in cpuinfo_arm_decode_vendor_uarch()
117 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
132 cpuinfo_log_warning("unknown Broadcom CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); in cpuinfo_arm_decode_vendor_uarch()
138 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
149 cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); in cpuinfo_arm_decode_vendor_uarch()
155 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
[all …]
|
| D | api.h | 89 uint32_t midr,
99 uint32_t midr,
114 uint32_t midr,
|
| D | cache.c | 13 uint32_t midr, in cpuinfo_arm_decode_cache() argument
25 switch (midr_get_part(midr) >> 8) { in cpuinfo_arm_decode_cache()
514 if (midr_is_qualcomm_cortex_a53_silver(midr)) { in cpuinfo_arm_decode_cache()
702 if (midr_is_qualcomm_cortex_a55_silver(midr)) { in cpuinfo_arm_decode_cache()
1013 switch (midr) { in cpuinfo_arm_decode_cache()
1318 if (midr_is_kryo_silver(midr)) { in cpuinfo_arm_decode_cache()
|
| /external/cpuinfo/src/arm/linux/ |
| D | clusters.c | 199 …if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_I… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
203 i, midr_get_implementer(processors[i].midr), midr_get_implementer(cluster_midr)); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
207 cluster_midr = midr_copy_implementer(cluster_midr, processors[i].midr); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
214 …if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_VARIA… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
218 i, midr_get_variant(processors[i].midr), midr_get_variant(cluster_midr)); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
222 cluster_midr = midr_copy_variant(cluster_midr, processors[i].midr); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
229 …if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_PART_MAS… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
233 i, midr_get_part(processors[i].midr), midr_get_part(cluster_midr)); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
237 cluster_midr = midr_copy_part(cluster_midr, processors[i].midr); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
244 …if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_REVI… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
[all …]
|
| D | midr.c | 556 … if ((processors[cluster_leader].midr ^ cluster_configs[c].cluster_midr[cluster]) & midr_mask) { in cpuinfo_arm_linux_detect_cluster_midr_by_chipset()
558 processors[cluster_leader].midr, cluster_configs[c].cluster_midr[cluster]); in cpuinfo_arm_linux_detect_cluster_midr_by_chipset()
567 processors[cluster_leader].midr = cluster_configs[c].cluster_midr[cluster]; in cpuinfo_arm_linux_detect_cluster_midr_by_chipset()
616 const uint32_t big_midr = processors[processors[last_processor_with_midr].package_leader_id].midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
650 const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic() local
651 if ((processors[cluster_leader].midr ^ midr) & midr_mask) { in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
654 processors[cluster_leader].midr, cluster_leader, midr); in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
667 const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic() local
668 cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, cluster_leader, midr); in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
670 processors[cluster_leader].midr = midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
[all …]
|
| D | aarch32-isa.c | 30 uint32_t midr, in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo() argument
63 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
84 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
101 if (architecture_version == 7 && midr_is_arm11(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
134 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
172 if (architecture_version >= 7 || midr_is_arm1156(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
184 …tures & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || midr_is_krait(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
223 …features & CPUINFO_ARM_LINUX_FEATURE_VFPV4) || midr_is_cortex_a9(midr) || midr_is_scorpion(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
|
| D | api.h | 152 uint32_t midr; member
218 if (processor_i->midr == processor_j->midr) { in cpuinfo_arm_linux_processor_equals()
219 if (midr_is_cortex_a53(processor_i->midr)) { in cpuinfo_arm_linux_processor_equals()
250 if (processor_i->midr != processor_j->midr) { in cpuinfo_arm_linux_processor_not_equals()
274 uint32_t midr,
283 uint32_t midr,
|
| D | init.c | 74 const uint32_t midr_a = processor_a->midr; in cmp_arm_linux_processor()
75 const uint32_t midr_b = processor_b->midr; in cmp_arm_linux_processor()
187 i, arm_linux_processors[i].midr); in cpuinfo_arm_linux_init()
209 last_midr = arm_linux_processors[i].midr; in cpuinfo_arm_linux_init()
368 arm_linux_processors[cluster_leader].midr, in cpuinfo_arm_linux_init()
378 arm_linux_processors[i].midr = arm_linux_processors[cluster_leader].midr; in cpuinfo_arm_linux_init()
389 i, arm_linux_processors[i].midr, arm_linux_processors[i].max_frequency); in cpuinfo_arm_linux_init()
399 …i, arm_linux_processors[i].system_processor_id, arm_linux_processors[i].midr, arm_linux_processors… in cpuinfo_arm_linux_init()
479 .midr = arm_linux_processors[i].midr, in cpuinfo_arm_linux_init()
499 cores[i].midr = arm_linux_processors[i].midr; in cpuinfo_arm_linux_init()
[all …]
|
| D | cpuinfo.c | 320 processor->midr = midr_set_architecture(processor->midr, UINT32_C(0xF)); in parse_cpu_architecture()
396 processor->midr = midr_set_architecture(processor->midr, midr_architecture); in parse_cpu_architecture()
445 processor->midr = midr_set_part(processor->midr, cpu_part); in parse_cpu_part()
499 processor->midr = midr_set_implementer(processor->midr, cpu_implementer); in parse_cpu_implementer()
543 processor->midr = midr_set_variant(processor->midr, cpu_variant); in parse_cpu_variant()
567 processor->midr = midr_set_revision(processor->midr, cpu_revision); in parse_cpu_revision()
|
| D | aarch64-isa.c | 9 uint32_t midr, in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo() argument
53 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
74 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
|
| /external/u-boot/board/renesas/condor/ |
| D | condor.c | 44 unsigned long midr, cputype; in reset_cpu() local
46 asm volatile("mrs %0, midr_el1" : "=r" (midr)); in reset_cpu()
47 cputype = (midr >> 4) & 0xfff; in reset_cpu()
|
| /external/u-boot/board/renesas/ebisu/ |
| D | ebisu.c | 55 unsigned long midr, cputype; in reset_cpu() local
57 asm volatile("mrs %0, midr_el1" : "=r" (midr)); in reset_cpu()
58 cputype = (midr >> 4) & 0xfff; in reset_cpu()
|
| /external/u-boot/board/renesas/eagle/ |
| D | eagle.c | 79 unsigned long midr, cputype; in reset_cpu() local
81 asm volatile("mrs %0, midr_el1" : "=r" (midr)); in reset_cpu()
82 cputype = (midr >> 4) & 0xfff; in reset_cpu()
|
| /external/u-boot/board/renesas/draak/ |
| D | draak.c | 82 unsigned long midr, cputype; in reset_cpu() local
84 asm volatile("mrs %0, midr_el1" : "=r" (midr)); in reset_cpu()
85 cputype = (midr >> 4) & 0xfff; in reset_cpu()
|
| /external/arm-trusted-firmware/lib/cpus/aarch64/ |
| D | cpuamu.c | 22 unsigned int midr, midr_mask; in midr_match() local
24 midr = (unsigned int)read_midr(); in midr_match()
27 return ((midr & midr_mask) == (cpu_midr & midr_mask)); in midr_match()
|
| /external/u-boot/board/highbank/ |
| D | highbank.c | 120 uint32_t midr; in is_highbank() local
122 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); in is_highbank()
124 return (midr & 0xfff0) == 0xc090; in is_highbank()
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/ |
| D | flowctrl.h | 84 void tegra_fc_cluster_idle(uint32_t midr);
86 void tegra_fc_cluster_powerdn(uint32_t midr);
93 void tegra_fc_soc_powerdn(uint32_t midr);
|
| /external/XNNPACK/third_party/ |
| D | cpuinfo.patch | 266 #include <arm/midr.h>
284 if (midr_is_qualcomm_cortex_a55_silver(midr)) {
604 diff --git src/arm/linux/midr.c src/arm/linux/midr.c
606 --- src/arm/linux/midr.c
607 +++ src/arm/linux/midr.c
630 - midr = processors[i].midr;
631 + midr = processors[i].midr;
633 cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, i, midr);
657 diff --git src/arm/midr.h src/arm/midr.h
659 --- src/arm/midr.h
[all …]
|
| /external/XNNPACK/cmake/ |
| D | cpuinfo.patch | 266 #include <arm/midr.h>
284 if (midr_is_qualcomm_cortex_a55_silver(midr)) {
604 diff --git src/arm/linux/midr.c src/arm/linux/midr.c
606 --- src/arm/linux/midr.c
607 +++ src/arm/linux/midr.c
630 - midr = processors[i].midr;
631 + midr = processors[i].midr;
633 cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, i, midr);
657 diff --git src/arm/midr.h src/arm/midr.h
659 --- src/arm/midr.h
[all …]
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hikey_bl2_setup.c | 224 u_register_t midr; in hikey_boardid_init() local
226 midr = read_midr(); in hikey_boardid_init()
227 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); in hikey_boardid_init()
229 (unsigned int)midr); in hikey_boardid_init()
|
| /external/cpuinfo/test/mock/ |
| D | meizu-pro-7-plus.cc | 210 TEST(CORES, midr) { in TEST() argument
215 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_core(i)->midr); in TEST()
221 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr); in TEST()
227 ASSERT_EQ(UINT32_C(0x410FD041), cpuinfo_get_core(i)->midr); in TEST()
362 TEST(CLUSTERS, midr) { in TEST() argument
366 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_cluster(i)->midr); in TEST()
369 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr); in TEST()
372 ASSERT_EQ(UINT32_C(0x410FD041), cpuinfo_get_cluster(i)->midr); in TEST()
|
| D | galaxy-s5-global.cc | 190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x412FC0F3), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FC073), cpuinfo_get_core(i)->midr); in TEST()
305 TEST(CLUSTERS, midr) { in TEST() argument
309 ASSERT_EQ(UINT32_C(0x412FC0F3), cpuinfo_get_cluster(i)->midr); in TEST()
312 ASSERT_EQ(UINT32_C(0x410FC073), cpuinfo_get_cluster(i)->midr); in TEST()
|
| D | lenovo-vibe-x2.cc | 171 TEST(CORES, midr) { in TEST() argument
178 ASSERT_EQ(UINT32_C(0x410FC0E0), cpuinfo_get_core(i)->midr); in TEST()
184 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_core(i)->midr); in TEST()
286 TEST(CLUSTERS, midr) { in TEST() argument
290 ASSERT_EQ(UINT32_C(0x410FC0E0), cpuinfo_get_cluster(i)->midr); in TEST()
293 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_cluster(i)->midr); in TEST()
|
| D | huawei-honor-6.cc | 190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x413FC0F3), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_core(i)->midr); in TEST()
305 TEST(CLUSTERS, midr) { in TEST() argument
309 ASSERT_EQ(UINT32_C(0x413FC0F3), cpuinfo_get_cluster(i)->midr); in TEST()
312 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_cluster(i)->midr); in TEST()
|