Home
last modified time | relevance | path

Searched refs:mmio_clrbits_32 (Results 1 – 25 of 62) sorted by relevance

123

/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc.c45 mmio_clrbits_32(reg, SW_NO_WAIT_Q); in spm_enable_cpu_auto_off()
58 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); in spm_set_cpu_power_off()
65 mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q); in spm_enable_cluster_auto_off()
66 mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0)); in spm_enable_cluster_auto_off()
68 mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN); in spm_enable_cluster_auto_off()
70 mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON); in spm_enable_cluster_auto_off()
168 mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
170 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
171 mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
172 mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
[all …]
/external/arm-trusted-firmware/plat/allwinner/sun50i_a64/
Dsunxi_power.c45 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
52 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
60 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc()
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc()
75 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); in sunxi_turn_off_soc()
78 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); in sunxi_turn_off_soc()
81 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); in sunxi_turn_off_soc()
82 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); in sunxi_turn_off_soc()
/external/arm-trusted-firmware/plat/imx/imx8m/
Dgpc_common.c50 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on()
52 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
63 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
78 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
81 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
100 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
101 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
104 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
117 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
149 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); in imx_set_cluster_powerdown()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c160 mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
161 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
162 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
163 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
164 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
165 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
166 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
168 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
169 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
170 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dgpc.c40 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
60 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
61 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
62 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
95 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
106 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); in imx_set_cluster_powerdown()
160 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); in imx_gpc_init()
167 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
168 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
119 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
120 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
152 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
153 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
154 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
Dhikey960_bl2_setup.c89 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
94 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
95 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
121 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
127 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
128 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
129 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_cpu_ops.c56 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_off()
65 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_off()
92 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
94 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
100 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); in sunxi_cpu_on()
/external/arm-trusted-firmware/plat/intel/soc/common/soc/
Dsocfpga_reset_manager.c18 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), in deassert_peripheral_reset()
37 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset()
47 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset()
71 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), in deassert_peripheral_reset()
108 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); in socfpga_bridges_enable()
143 mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
/external/arm-trusted-firmware/drivers/st/gpio/
Dstm32_gpio.c212 mmio_clrbits_32(base + GPIO_MODE_OFFSET, in set_gpio()
220 mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); in set_gpio()
223 mmio_clrbits_32(base + GPIO_SPEED_OFFSET, in set_gpio()
227 mmio_clrbits_32(base + GPIO_PUPD_OFFSET, in set_gpio()
232 mmio_clrbits_32(base + GPIO_AFRL_OFFSET, in set_gpio()
237 mmio_clrbits_32(base + GPIO_AFRH_OFFSET, in set_gpio()
271 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); in set_gpio_secure_cfg()
/external/arm-trusted-firmware/drivers/st/ddr/
Dstm32mp1_ddr.c387 mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in stm32mp1_start_sw_done()
631 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
650 mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
666 mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
678 mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); in stm32mp1_refresh_disable()
679 mmio_clrbits_32((uintptr_t)&ctl->dfimisc, in stm32mp1_refresh_disable()
689 mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, in stm32mp1_refresh_restore()
756 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
757 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
762 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/common/drivers/ccu/
Dncore_ccu.c105 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1), in bypass_ocram_firewall()
107 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2), in bypass_ocram_firewall()
109 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3), in bypass_ocram_firewall()
111 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), in bypass_ocram_firewall()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/
Dmtcmos.c138 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); in mtcmos_ctrl_little_off()
144 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); in mtcmos_ctrl_little_off()
146 mmio_clrbits_32(reg_pwr_con, PWR_ON); in mtcmos_ctrl_little_off()
147 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); in mtcmos_ctrl_little_off()
270 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/
Dmtgpio.c229 mmio_clrbits_32(pupd_addr, 3U << pupd_offset); in mt_set_gpio_pull_enable_chip()
231 mmio_clrbits_32(pullen_addr, in mt_set_gpio_pull_enable_chip()
242 mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1)); in mt_set_gpio_pull_enable_chip()
251 mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1)); in mt_set_gpio_pull_enable_chip()
255 mmio_clrbits_32(pupd_addr, 1U << pupd_offset); in mt_set_gpio_pull_enable_chip()
304 mmio_clrbits_32(pullsel_addr, in mt_set_gpio_pull_select_chip()
309 mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 2)); in mt_set_gpio_pull_select_chip()
318 mmio_clrbits_32(pullsel_addr, in mt_set_gpio_pull_select_chip()
/external/arm-trusted-firmware/plat/marvell/a3700/common/
Dplat_pm.c270 mmio_clrbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()
313 mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_CPU_VDDV_OFF_EN); in a3700_set_gen_pwr_off_option()
324 mmio_clrbits_32(MVEBU_NB_CLOCK_SEL_REG, MVEBU_A53_CPU_CLK_SEL); in a3700_set_gen_pwr_off_option()
415 mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_AVS_DISABLE_MODE); in a3700_pwr_dn_avs()
494 mmio_clrbits_32(MVEBU_NB_GPIO_IRQ_MASK_2_REG, BIT(gpio - 32)); in a3700_pm_en_nb_gpio()
500 mmio_clrbits_32(MVEBU_NB_GPIO_IRQ_MASK_1_REG, BIT(gpio)); in a3700_pm_en_nb_gpio()
529 mmio_clrbits_32(MVEBU_SB_GPIO_IRQ_MASK_REG, BIT(gpio)); in a3700_pm_en_sb_gpio()
548 mmio_clrbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_UART1_SEL); in a3700_pm_src_uart1()
619 mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, in a3700_pm_clear_lp_flag()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/
Dgpc.c44 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | in imx_gpc_init()
86 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
87 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port()
77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
Dsuspend.c27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main()
55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c257 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); in data_training()
303 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); in data_training()
351 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); in data_training()
384 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); in data_training()
398 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); in data_training()
419 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); in data_training()
423 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
615 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
634 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
684 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE); in pmusram_enable_watchdog()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm_suspend.c285 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); in bigcore_pll_on()
291 mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); in bigcore_pll_off()
293 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); in bigcore_pll_off()
Dspm_hotplug.c246 mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); in spm_hotplug_on()
267 mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); in spm_hotplug_off()
/external/arm-trusted-firmware/plat/mediatek/mt6795/
Dscu.c25 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, in enable_scu()
28 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, in enable_scu()
/external/arm-trusted-firmware/plat/mediatek/mt8173/
Dscu.c25 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in enable_scu()
28 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in enable_scu()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/
Dspm_suspend.c216 mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2); in spm_enable_armpll_l()
228 mmio_clrbits_32(ARMPLL_L_CON0, 0x1); in spm_disable_armpll_l()
234 mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1); in spm_disable_armpll_l()
/external/arm-trusted-firmware/drivers/st/i2c/
Dstm32_i2c.c70 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); in i2c_config_analog_filter()
73 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_ANFOFF); in i2c_config_analog_filter()
164 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); in stm32_i2c_init()
171 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_OAR1, I2C_OAR1_OA1EN); in stm32_i2c_init()
198 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_OAR2, I2C_DUALADDRESS_ENABLE); in stm32_i2c_init()
318 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2); in i2c_ack_failed()
642 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2); in i2c_write()
811 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2); in i2c_read()

123