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Searched refs:pll_id (Results 1 – 22 of 22) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c53 static void set_pll_slow_mode(uint32_t pll_id) in set_pll_slow_mode() argument
55 if (pll_id == PPLL_ID) in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
62 static void set_pll_normal_mode(uint32_t pll_id) in set_pll_normal_mode() argument
64 if (pll_id == PPLL_ID) in set_pll_normal_mode()
68 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); in set_pll_normal_mode()
71 static void set_pll_bypass(uint32_t pll_id) in set_pll_bypass() argument
73 if (pll_id == PPLL_ID) in set_pll_bypass()
78 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); in set_pll_bypass()
81 static void _pll_suspend(uint32_t pll_id) in _pll_suspend() argument
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Dsoc.h16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/
Dsoc.c125 static void plls_suspend(uint32_t pll_id) in plls_suspend() argument
127 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in plls_suspend()
128 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in plls_suspend()
129 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in plls_suspend()
130 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in plls_suspend()
132 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); in plls_suspend()
133 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); in plls_suspend()
/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c270 static inline void pm_pll_wait_lock(uint32_t pll_id) in pm_pll_wait_lock() argument
275 if (mmio_read_32(CRU_BASE + PLL_CONS(pll_id, 1)) & in pm_pll_wait_lock()
281 ERROR("lock-pll: %d\n", pll_id); in pm_pll_wait_lock()
284 static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd) in pll_pwr_dwn() argument
286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
289 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
292 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
340 static inline void pll_suspend(uint32_t pll_id) in pll_suspend() argument
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
349 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
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Dpmu.h116 #define PLL_IS_NORM_MODE(mode, pll_id) \ argument
117 ((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0)
/external/u-boot/drivers/clk/rockchip/
Dclk_pll.c182 void __iomem *base, ulong pll_id, in rk3036_pll_set_rate() argument
250 void __iomem *base, ulong pll_id) in rk3036_pll_get_rate() argument
299 ulong pll_id) in rockchip_pll_get_rate() argument
306 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
310 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
314 __func__, pll_id); in rockchip_pll_get_rate()
320 void __iomem *base, ulong pll_id, in rockchip_pll_set_rate() argument
325 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
331 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
335 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
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Dclk_px30.c90 enum px30_pll_id pll_id);
201 enum px30_pll_id pll_id, in rkclk_set_pll() argument
227 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
228 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); in rkclk_set_pll()
249 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
250 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); in rkclk_set_pll()
256 enum px30_pll_id pll_id) in rkclk_pll_get_rate() argument
262 shift = pll_mode_shift[pll_id]; in rkclk_pll_get_rate()
263 mask = pll_mode_mask[pll_id]; in rkclk_pll_get_rate()
1095 enum px30_pll_id pll_id) in px30_clk_get_pll_rate() argument
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Dclk_rk3036.c47 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
174 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
175 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
Dclk_rk322x.c44 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
175 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
176 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
Dclk_rk3188.c88 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
89 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
230 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
231 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
Dclk_rk3128.c41 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
243 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
244 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
Dclk_rk3368.c62 enum rk3368_pll_id pll_id) in rkclk_pll_get_rate() argument
66 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
88 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
91 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
Dclk_rv1108.c68 int pll_id = rv1108_pll_id(clk_id); in rkclk_set_pll() local
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
122 int pll_id = rv1108_pll_id(clk_id); in rkclk_pll_get_rate() local
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
Dclk_rk3288.c147 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
148 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
542 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
543 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
/external/u-boot/drivers/clk/
Dclk_stm32mp1.c855 int pll_id) in pll_get_fref_ck() argument
863 selr = readl(priv->base + pll[pll_id].rckxselr); in pll_get_fref_ck()
866 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); in pll_get_fref_ck()
878 int pll_id) in pll_get_fvco() argument
885 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); in pll_get_fvco()
886 fracr = readl(priv->base + pll[pll_id].pllxfracr); in pll_get_fvco()
891 refclk = pll_get_fref_ck(priv, pll_id); in pll_get_fvco()
912 int pll_id, int div_id) in stm32mp1_read_pll_freq() argument
922 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); in stm32mp1_read_pll_freq()
925 dfout = pll_get_fvco(priv, pll_id) / (divy + 1); in stm32mp1_read_pll_freq()
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/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/
Dsoc.c105 static void pll_save(uint32_t pll_id) in pll_save() argument
107 uint32_t *pll = slp_data.pll_con[pll_id]; in pll_save()
109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save()
110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save()
111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save()
112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
/external/arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/
Dpmu.c855 static inline void pm_pll_wait_lock(uint32_t pll_base, uint32_t pll_id) in pm_pll_wait_lock() argument
867 ERROR("Can't wait pll:%d lock\n", pll_id); in pm_pll_wait_lock()
870 static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd) in pll_pwr_ctr() argument
882 static inline void pll_set_mode(uint32_t pll_id, uint32_t mode) in pll_set_mode() argument
884 uint32_t val = BITS_WITH_WMASK(mode, 0x3, PLL_MODE_SHIFT(pll_id)); in pll_set_mode()
886 if (pll_id != GPLL_ID) in pll_set_mode()
893 static inline void pll_suspend(uint32_t pll_id) in pll_suspend() argument
898 if (pll_id != GPLL_ID) in pll_suspend()
899 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
905 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c646 __pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src) in pmusram_restore_pll() argument
648 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
650 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
651 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
652 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
653 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
654 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
656 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
658 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
/external/arm-trusted-firmware/drivers/st/clk/
Dstm32mp1_clk.c709 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, in stm32mp1_read_pll_freq() argument
712 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq()
1231 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, in stm32mp1_check_pll_conf() argument
1235 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_check_pll_conf()
1303 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) in stm32mp1_pll_start() argument
1305 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_pll_start()
1315 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) in stm32mp1_pll_output() argument
1317 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_pll_output()
1325 pll_id, pllxcr, mmio_read_32(pllxcr)); in stm32mp1_pll_output()
1336 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) in stm32mp1_pll_stop() argument
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/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dsdram_px30.h71 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
Dsdram_rk3328.h51 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dpmu.c565 uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; in clst_pwr_domain_suspend() local
571 pll_id = ALPLL_ID; in clst_pwr_domain_suspend()
574 pll_id = ABPLL_ID; in clst_pwr_domain_suspend()
586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
589 clst_warmboot_data[pll_id] = PMU_CLST_RET; in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
601 clst_warmboot_data[pll_id] = 0; in clst_pwr_domain_suspend()
609 uint32_t pll_id, pll_st; in clst_pwr_domain_resume() local
615 pll_id = ALPLL_ID; in clst_pwr_domain_resume()
617 pll_id = ABPLL_ID; in clst_pwr_domain_resume()
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