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Searched refs:read_midr (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/arch/arm/include/asm/armv8/
Dcpu.h12 static inline unsigned int read_midr(void) in read_midr() function
21 #define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
23 #define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
25 #define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
/external/arm-trusted-firmware/lib/cpus/aarch64/
Dcpuamu.c24 midr = (unsigned int)read_midr(); in midr_match()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_psci_handlers.c322 impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_on_finish()
382 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
Dplat_setup.c181 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in plat_early_platform_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/
Dmce.c115 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in mce_get_curr_cpu_ari_base()
135 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & in mce_get_curr_cpu_ops()
Dnvg.c207 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in nvg_online_core()
Dari.c330 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in ari_online_core()
/external/arm-trusted-firmware/lib/el3_runtime/aarch32/
Dcontext_mgmt.c258 write_vpidr(read_midr()); in cm_prepare_el3_exit()
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_bl2_setup.c226 midr = read_midr(); in hikey_boardid_init()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/flowctrl/
Dflowctrl.c166 read_midr() == CORTEX_A53_MIDR); in tegra_fc_cluster_powerdn()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_bl31_setup.c273 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_psci_handlers.c462 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
/external/arm-trusted-firmware/include/arch/aarch64/
Darch_helpers.h542 #define read_midr() read_midr_el1() macro
/external/arm-trusted-firmware/plat/renesas/rcar/
Dbl2_plat_setup.c711 reg = read_midr(); in bl2_el3_early_platform_setup()