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Searched refs:rt2 (Results 1 – 25 of 55) sorted by relevance

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/external/e2fsprogs/lib/ss/
Drequest_tbl.c55 register ssrt **rt1, **rt2; in ss_delete_request_table() local
60 for (rt2 = rt1; *rt1; rt1++) { in ss_delete_request_table()
62 *rt2++ = *rt1; in ss_delete_request_table()
66 *rt2 = (ssrt *)NULL; in ss_delete_request_table()
/external/tensorflow/tensorflow/python/ops/ragged/
Dragged_tensor_bounding_shape_op_test.py39 rt2 = ragged_tensor.RaggedTensor.from_row_splits(values, [0, 7])
42 self.assertAllEqual(rt2.bounding_shape(), [1, 7])
48 rt2 = ragged_tensor.RaggedTensor.from_row_splits(values, [0, 7])
51 self.assertAllEqual(rt2.bounding_shape(), [1, 7, 2])
Dragged_range_op_test.py35 rt2 = ragged_math_ops.range([0, 5, 8], [3, 3, 12])
36 self.assertAllEqual(rt2, [[0, 1, 2], [], [8, 9, 10, 11]])
96 rt2 = ragged_math_ops.range([0, 5, 5], [0, 3, 5], -1)
98 self.assertAllEqual(rt2, [[], [5, 4], []])
Dragged_tensor_test.py138 rt2 = RaggedTensor.from_row_lengths(values, row_lengths=[4, 0, 3, 1, 0])
143 for rt in (rt1, rt2, rt3, rt4, rt5):
145 del rt1, rt2, rt3, rt4, rt5
389 rt2 = RaggedTensor.from_row_splits(values, splits2)
394 self.assertEqual(rt2.row_splits.dtype, dtypes.int64)
510 rt2 = RaggedTensor.from_uniform_row_length(ph_values, ph_rowlen)
513 self.assertAllEqual(rt2, [[1, 2, 3], [4, 5, 6]])
517 self.assertEqual(rt2.shape.as_list(), [2, 3])
521 self.assertEqual(rt2.shape.as_list(), [None, None])
709 rt2 = RaggedTensor.from_value_rowids(values, value_rowids)
[all …]
Dragged_to_sparse_op_test.py188 rt2 = ragged_factory_ops.constant(
190 rt = ragged_functional_ops.map_flat_values(math_ops.add, rt1, rt2 * 2.0)
194 [rt1.flat_values, rt2.flat_values])
/external/llvm/test/Verifier/
Drecursive-type-3.ll3 %rt2 = type { i32, { i8, %rt2*, i8 }, i32 }
9 %0 = alloca %rt2
Drecursive-type-1.ll3 %rt2 = type { i32, { i8, %rt2, i8 }, i32 }
10 %0 = alloca %rt2
Drecursive-type-2.ll3 %rt1 = type { i32, { i8, %rt2, i8 }, i32 }
4 %rt2 = type { i64, { i6, %rt3 } }
12 %0 = alloca %rt2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Verifier/
Drecursive-type-3.ll3 %rt2 = type { i32, { i8, %rt2*, i8 }, i32 }
9 %0 = alloca %rt2
Drecursive-type-1.ll3 %rt2 = type { i32, { i8, %rt2, i8 }, i32 }
10 %0 = alloca %rt2
Drecursive-type-2.ll3 %rt1 = type { i32, { i8, %rt2, i8 }, i32 }
4 %rt2 = type { i64, { i6, %rt3 } }
12 %0 = alloca %rt2
/external/llvm/test/CodeGen/AArch64/
Dreturnaddr.ll11 define i8* @rt2() nounwind readnone {
13 ; CHECK-LABEL: rt2:
Darm64-returnaddr.ll12 define i8* @rt2() nounwind readnone {
14 ; CHECK-LABEL: rt2:
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dreturnaddr.ll11 define i8* @rt2() nounwind readnone {
13 ; CHECK-LABEL: rt2:
Darm64-returnaddr.ll12 define i8* @rt2() nounwind readnone {
14 ; CHECK-LABEL: rt2:
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Darm-returnaddr.ll16 define i8* @rt2() nounwind readnone {
18 ; CHECK-LABEL: rt2:
/external/llvm/test/CodeGen/ARM/
Darm-returnaddr.ll16 define i8* @rt2() nounwind readnone {
18 ; CHECK-LABEL: rt2:
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.cc1677 Register rt2, in Delegate() argument
1686 temps.Include(rt, rt2); in Delegate()
1689 ldrd(rt, rt2, MemOperandComputationHelper(cond, scratch, location, mask)); in Delegate()
1693 Assembler::Delegate(type, instruction, cond, rt, rt2, location); in Delegate()
1898 Register rt2, in Delegate() argument
1919 if (((rt.GetCode() + 1) % kNumberOfRegisters) != rt2.GetCode()) { in Delegate()
1950 if (!rt2.Is(rn)) temps.Include(rt2); in Delegate()
1965 rt2, in Delegate()
1975 if (!rt2.Is(rn)) temps.Include(rt2); in Delegate()
1990 rt2, in Delegate()
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/external/v8/src/execution/arm64/
Dsimulator-arm64.cc1956 unsigned rt2 = instr->Rt2(); in LoadStorePairHelper() local
1993 DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2)); in LoadStorePairHelper()
2001 set_wreg_no_log(rt2, MemoryRead<uint32_t>(address2)); in LoadStorePairHelper()
2007 set_sreg_no_log(rt2, MemoryRead<float>(address2)); in LoadStorePairHelper()
2013 set_xreg_no_log(rt2, MemoryRead<uint64_t>(address2)); in LoadStorePairHelper()
2019 set_dreg_no_log(rt2, MemoryRead<double>(address2)); in LoadStorePairHelper()
2025 set_qreg(rt2, MemoryRead<qreg_t>(address2), NoRegLog); in LoadStorePairHelper()
2031 set_xreg_no_log(rt2, MemoryRead<int32_t>(address2)); in LoadStorePairHelper()
2037 MemoryWrite<uint32_t>(address2, wreg(rt2)); in LoadStorePairHelper()
2043 MemoryWrite<float>(address2, sreg(rt2)); in LoadStorePairHelper()
[all …]
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc1756 unsigned rt2 = instr->GetRt2(); in LoadStorePairHelper() local
1766 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2)); in LoadStorePairHelper()
1773 WriteWRegister(rt2, Memory::Read<uint32_t>(address2), NoRegLog); in LoadStorePairHelper()
1778 WriteSRegister(rt2, Memory::Read<float>(address2), NoRegLog); in LoadStorePairHelper()
1783 WriteXRegister(rt2, Memory::Read<uint64_t>(address2), NoRegLog); in LoadStorePairHelper()
1788 WriteDRegister(rt2, Memory::Read<double>(address2), NoRegLog); in LoadStorePairHelper()
1793 WriteQRegister(rt2, Memory::Read<qreg_t>(address2), NoRegLog); in LoadStorePairHelper()
1798 WriteXRegister(rt2, Memory::Read<int32_t>(address2), NoRegLog); in LoadStorePairHelper()
1803 Memory::Write<uint32_t>(address2, ReadWRegister(rt2)); in LoadStorePairHelper()
1808 Memory::Write<float>(address2, ReadSRegister(rt2)); in LoadStorePairHelper()
[all …]
Dassembler-aarch64.cc1097 const CPURegister& rt2, in ldp() argument
1099 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2)); in ldp()
1104 const CPURegister& rt2, in stp() argument
1106 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2)); in stp()
1119 const CPURegister& rt2, in LoadStorePair() argument
1122 VIXL_ASSERT(CPUHas(rt, rt2)); in LoadStorePair()
1125 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2)); in LoadStorePair()
1126 VIXL_ASSERT(AreSameSizeAndType(rt, rt2)); in LoadStorePair()
1130 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) | in LoadStorePair()
1149 const CPURegister& rt2, in ldnp() argument
[all …]
Dassembler-aarch64.h1311 const CPURegister& rt2,
1316 const CPURegister& rt2,
1324 const CPURegister& rt2,
1329 const CPURegister& rt2,
1365 const Register& rt2,
1369 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src);
1392 const Register& rt2,
1396 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src);
1474 const Register& rt2,
1481 const Register& rt2,
[all …]
Dmacro-assembler-aarch64.h62 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
63 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
64 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
788 const CPURegister& rt2,
1647 void Ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) { in Ldaxp() argument
1649 VIXL_ASSERT(!rt.Aliases(rt2)); in Ldaxp()
1651 ldaxp(rt, rt2, src); in Ldaxp()
1707 const Register& rt2, \
1711 ASM(rs, rs2, rt, rt2, src); \
1835 const CPURegister& rt2, in Ldnp() argument
[all …]
/external/pdfium/xfa/fxfa/
Dcxfa_ffpageview.cpp426 const CFX_RectF& rt2 = arg2->GetWidget()->GetWidgetRect(); in OrderContainer() local
427 if (rt1.top - rt2.top >= kXFAWidgetPrecision) in OrderContainer()
428 return rt1.top < rt2.top; in OrderContainer()
429 return rt1.left < rt2.left; in OrderContainer()
/external/tensorflow/tensorflow/python/keras/
Dmetrics_test.py394 rt2 = ragged_factory_ops.constant([[1], [2], [3], [4]])
395 update_op = acc_obj.update_state(rt1, rt2)
402 rt2 = ragged_factory_ops.constant([[2], [0]])
404 result_t = acc_obj(rt1, rt2, sample_weight=sw_ragged)
446 rt2 = ragged_factory_ops.constant([[1], [0]])
447 update_op = acc_obj.update_state(rt1, rt2)
455 rt2 = ragged_factory_ops.constant([[1], [0]])
457 result_t = acc_obj(rt1, rt2)
471 rt2 = ragged_factory_ops.constant([[0.9], [0.6], [0.4], [0.8]])
472 result_t = acc_obj(rt1, rt2)
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