Home
last modified time | relevance | path

Searched refs:zero_reg (Results 1 – 25 of 42) sorted by relevance

12

/external/libaom/libaom/aom_dsp/x86/
Dvariance_impl_avx2.c72 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \
73 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \
88 res_cmp = _mm256_cmpgt_epi16(zero_reg, sum_reg); \
172 __m256i zero_reg; in aom_sub_pixel_variance32xh_avx2() local
176 zero_reg = _mm256_set1_epi16(0); in aom_sub_pixel_variance32xh_avx2()
184 MERGE_WITH_SRC(src_reg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
196 MERGE_WITH_SRC(src_reg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
226 MERGE_WITH_SRC(src_reg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
246 MERGE_WITH_SRC(src_avg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
310 MERGE_WITH_SRC(src_pack, zero_reg) in aom_sub_pixel_variance32xh_avx2()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc84 /* 54*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
92 /* 72*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
122 /* 129*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
130 /* 147*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
157 /* 200*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
183 /* 255*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
202 /* 294*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
229 /* 349*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
256 /* 407*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
275 /* 446*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
[all …]
DARMGenGlobalISel.inc790 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
814 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
838 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
862 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
886 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
910 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
934 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
958 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
994 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1030 GIR_AddRegister, /*InsnID*/0, ::zero_reg,
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dvariance_avx2.c190 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \
191 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \
206 res_cmp = _mm256_cmpgt_epi16(zero_reg, sum_reg); \
230 const __m256i zero_reg = _mm256_setzero_si256(); in spv32_x0_y0() local
239 exp_src_lo = _mm256_unpacklo_epi8(avg_reg, zero_reg); in spv32_x0_y0()
240 exp_src_hi = _mm256_unpackhi_epi8(avg_reg, zero_reg); in spv32_x0_y0()
243 exp_src_lo = _mm256_unpacklo_epi8(src_reg, zero_reg); in spv32_x0_y0()
244 exp_src_hi = _mm256_unpackhi_epi8(src_reg, zero_reg); in spv32_x0_y0()
259 const __m256i zero_reg = _mm256_setzero_si256(); in spv32_half_zero() local
270 exp_src_lo = _mm256_unpacklo_epi8(avg_reg, zero_reg); in spv32_half_zero()
[all …]
/external/libaom/libaom/av1/encoder/x86/
Derror_intrin_avx2.c93 const __m256i zero_reg = _mm256_setzero_si256(); in av1_block_error_avx2() local
110 exp_dqcoeff_lo = _mm256_unpacklo_epi32(dqcoeff_reg, zero_reg); in av1_block_error_avx2()
111 exp_dqcoeff_hi = _mm256_unpackhi_epi32(dqcoeff_reg, zero_reg); in av1_block_error_avx2()
113 exp_coeff_lo = _mm256_unpacklo_epi32(coeff_reg, zero_reg); in av1_block_error_avx2()
114 exp_coeff_hi = _mm256_unpackhi_epi32(coeff_reg, zero_reg); in av1_block_error_avx2()
/external/v8/src/codegen/mips/
Dmacro-assembler-mips.cc39 return rt.rm() == zero_reg; in IsZero()
192 Branch(&ok, eq, t8, Operand(zero_reg)); in RecordWriteField()
801 subu(rs, zero_reg, rt.rm()); in Neg()
926 subu(scratch, zero_reg, rt.rm()); in Ror()
946 lw(zero_reg, rs); in Pref()
1382 addiu(rd, zero_reg, j.immediate()); in li()
1384 ori(rd, zero_reg, j.immediate()); in li()
1544 Nor(scratch2, zero_reg, scratch3); in ShlPair()
1551 Branch(&done, eq, scratch1, Operand(zero_reg)); in ShlPair()
1553 mov(dst_low, zero_reg); in ShlPair()
[all …]
Dassembler-mips.cc165 zero_reg, at, v0, v1, a0, a1, a2, a3, t0, t1, t2, t3, t4, t5, t6, t7, in ToRegister()
653 Register nop_rt_reg = (type == 0) ? zero_reg : at; in IsNop()
655 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
1491 void Assembler::b(int16_t offset) { beq(zero_reg, zero_reg, offset); } in b()
1493 void Assembler::bal(int16_t offset) { bgezal(zero_reg, offset); } in bal()
1519 DCHECK(rt != zero_reg); in bgezc()
1525 DCHECK(rs != zero_reg); in bgeuc()
1526 DCHECK(rt != zero_reg); in bgeuc()
1533 DCHECK(rs != zero_reg); in bgec()
1534 DCHECK(rt != zero_reg); in bgec()
[all …]
Dmacro-assembler-mips.h193 Condition cond = al, Register rs = zero_reg, \
194 const Operand &rt = Operand(zero_reg), \
246 Register rs = zero_reg,
247 const Operand& rt = Operand(zero_reg)) {
697 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); } in mov()
Dregister-mips.h17 V(zero_reg) V(at) V(v0) V(v1) V(a0) V(a1) V(a2) V(a3) \
/external/v8/src/codegen/mips64/
Dmacro-assembler-mips64.cc39 return rt.rm() == zero_reg; in IsZero()
190 Branch(&ok, eq, t8, Operand(zero_reg)); in RecordWriteField()
937 dsubu(rs, zero_reg, rt.rm()); in Neg()
1156 dinsu_(dest, zero_reg, 32, 32); in ByteSwapUnsigned()
1597 daddiu(rd, zero_reg, (j.immediate() & kImm16Mask)); in LiLower32BitHelper()
1599 ori(rd, zero_reg, j.immediate() & kImm16Mask); in LiLower32BitHelper()
1729 ori(rd, zero_reg, j.immediate() & kImm16Mask); in li_optimized()
1736 ori(rd, zero_reg, j.immediate() & kImm16Mask); in li_optimized()
1759 daddiu(rd, zero_reg, j.immediate() & kImm16Mask); in li_optimized()
1767 daddiu(rd, zero_reg, j.immediate() & kImm16Mask); in li_optimized()
[all …]
Dassembler-mips64.cc140 zero_reg, at, v0, v1, a0, a1, a2, a3, a4, a5, a6, a7, t0, t1, t2, t3, in ToRegister()
603 Register nop_rt_reg = (type == 0) ? zero_reg : at; in IsNop()
605 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
1432 void Assembler::b(int16_t offset) { beq(zero_reg, zero_reg, offset); } in b()
1434 void Assembler::bal(int16_t offset) { bgezal(zero_reg, offset); } in bal()
1460 DCHECK(rt != zero_reg); in bgezc()
1466 DCHECK(rs != zero_reg); in bgeuc()
1467 DCHECK(rt != zero_reg); in bgeuc()
1474 DCHECK(rs != zero_reg); in bgec()
1475 DCHECK(rt != zero_reg); in bgec()
[all …]
Dmacro-assembler-mips64.h219 Condition cond = al, Register rs = zero_reg, \
220 const Operand &rt = Operand(zero_reg), \
269 Register rs = zero_reg,
270 const Operand& rt = Operand(zero_reg)) {
656 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); } in mov()
Dregister-mips64.h17 V(zero_reg) V(at) V(v0) V(v1) V(a0) V(a1) V(a2) V(a3) \
/external/v8/src/builtins/mips/
Dbuiltins-mips.cc405 __ Branch(&non_outermost_js, ne, t2, Operand(zero_reg)); in Generate_JSEntryVariant()
469 __ sw(zero_reg, MemOperand(t1)); in Generate_JSEntryVariant()
644 __ Branch(&prepare_step_in_if_stepping, ne, t1, Operand(zero_reg)); in Generate_ResumeGeneratorTrampoline()
679 __ Branch(&done_loop, lt, a3, Operand(zero_reg)); in Generate_ResumeGeneratorTrampoline()
826 __ Branch(&heal_optimized_code_slot, ne, scratch1, Operand(zero_reg)); in TailCallOptimizedCodeSlot()
910 __ Branch(&extra_wide, ne, scratch2, Operand(zero_reg)); in AdvanceBytecodeOffsetOrReturn()
1013 __ Branch(&has_optimized_code_or_marker, ne, t1, Operand(zero_reg)); in Generate_InterpreterEntryTrampoline()
1038 __ sh(zero_reg, FieldMemOperand(kInterpreterBytecodeArrayRegister, in Generate_InterpreterEntryTrampoline()
1072 __ Branch(&loop_header, ge, t0, Operand(zero_reg)); in Generate_InterpreterEntryTrampoline()
1082 Operand(zero_reg)); in Generate_InterpreterEntryTrampoline()
[all …]
/external/v8/src/builtins/mips64/
Dbuiltins-mips64.cc339 __ Branch(&prepare_step_in_if_stepping, ne, a5, Operand(zero_reg)); in Generate_ResumeGeneratorTrampoline()
376 __ Branch(&done_loop, lt, a3, Operand(zero_reg)); in Generate_ResumeGeneratorTrampoline()
560 __ Branch(&non_outermost_js, ne, s2, Operand(zero_reg)); in Generate_JSEntryVariant()
635 __ Sd(zero_reg, MemOperand(a5)); in Generate_JSEntryVariant()
842 __ Branch(&heal_optimized_code_slot, ne, a5, Operand(zero_reg)); in TailCallOptimizedCodeSlot()
928 __ Branch(&extra_wide, ne, scratch2, Operand(zero_reg)); in AdvanceBytecodeOffsetOrReturn()
1031 __ Branch(&has_optimized_code_or_marker, ne, t0, Operand(zero_reg)); in Generate_InterpreterEntryTrampoline()
1056 __ sh(zero_reg, FieldMemOperand(kInterpreterBytecodeArrayRegister, in Generate_InterpreterEntryTrampoline()
1090 __ Branch(&loop_header, ge, a4, Operand(zero_reg)); in Generate_InterpreterEntryTrampoline()
1100 Operand(zero_reg)); in Generate_InterpreterEntryTrampoline()
[all …]
/external/v8/src/regexp/mips64/
Dregexp-macro-assembler-mips64.cc280 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
289 BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
398 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
423 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); in CheckNotBackReference()
432 BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg)); in CheckNotBackReference()
482 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckCharacterAfterAnd()
491 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckNotCharacterAfterAnd()
540 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg)); in CheckBitInTable()
620 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); in CheckSpecialCharacterClass()
633 BranchOrBacktrack(on_no_match, ne, a0, Operand(zero_reg)); in CheckSpecialCharacterClass()
[all …]
/external/v8/src/regexp/mips/
Dregexp-macro-assembler-mips.cc244 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
253 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
362 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg)); in CheckNotBackReferenceIgnoreCase()
387 __ Branch(&fallthrough, le, a1, Operand(zero_reg)); in CheckNotBackReference()
396 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg)); in CheckNotBackReference()
452 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckCharacterAfterAnd()
461 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); in CheckNotCharacterAfterAnd()
510 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg)); in CheckBitInTable()
590 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); in CheckSpecialCharacterClass()
603 BranchOrBacktrack(on_no_match, ne, a0, Operand(zero_reg)); in CheckSpecialCharacterClass()
[all …]
/external/v8/src/compiler/backend/mips/
Dcode-generator-mips.cc55 return zero_reg; in InputOrZeroRegister()
341 __ BranchShort(&binop, eq, i.TempRegister(1), Operand(zero_reg)); \
362 __ BranchShort(&binop, eq, i.TempRegister(1), Operand(zero_reg)); \
392 __ BranchShort(&binop, eq, i.TempRegister(1), Operand(zero_reg)); \
421 __ BranchShort(&binop, eq, i.TempRegister(1), Operand(zero_reg)); \
434 __ BranchShort(&exchange, eq, i.TempRegister(1), Operand(zero_reg)); \
453 __ BranchShort(&exchange, eq, i.TempRegister(2), Operand(zero_reg)); \
470 Operand(zero_reg)); \
496 Operand(zero_reg)); \
619 RelocInfo::CODE_TARGET, ne, kScratchReg, Operand(zero_reg)); in BailoutIfDeoptimized()
[all …]
/external/v8/src/compiler/backend/mips64/
Dcode-generator-mips64.cc56 return zero_reg; in InputOrZeroRegister()
349 __ BranchShort(&binop, eq, i.TempRegister(1), Operand(zero_reg)); \
377 __ BranchShort(&binop, eq, i.TempRegister(1), Operand(zero_reg)); \
390 __ BranchShort(&exchange, eq, i.TempRegister(1), Operand(zero_reg)); \
416 __ BranchShort(&exchange, eq, i.TempRegister(2), Operand(zero_reg)); \
434 Operand(zero_reg)); \
467 Operand(zero_reg)); \
590 RelocInfo::CODE_TARGET, ne, kScratchReg, Operand(zero_reg)); in BailoutIfDeoptimized()
908 Operand(zero_reg)); in AssembleArchInstruction()
914 __ BranchShort(&done, eq, kScratchReg, Operand(zero_reg)); in AssembleArchInstruction()
[all …]
/external/v8/src/wasm/baseline/mips/
Dliftoff-assembler-mips.h138 assm->movz(tmp, reg, zero_reg); in EnsureNoAlias()
180 assm->TurboAssembler::Move(tmp.high_gp(), zero_reg); in ChangeEndiannessLoad()
188 assm->TurboAssembler::Move(tmp.high_gp(), zero_reg); in ChangeEndiannessLoad()
741 Sw(zero_reg, liftoff::GetStackSlot(start + offset)); in FillStackSlotsWithZero()
752 Sw(zero_reg, MemOperand(a0)); in FillStackSlotsWithZero()
767 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_divs()
776 Operand(zero_reg)); in emit_i32_divs()
783 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_divu()
789 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_rems()
795 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_remu()
[all …]
/external/v8/src/wasm/baseline/mips64/
Dliftoff-assembler-mips64.h700 Sd(zero_reg, liftoff::GetStackSlot(start + remainder)); in FillStackSlotsWithZero()
704 Sw(zero_reg, liftoff::GetStackSlot(start + remainder)); in FillStackSlotsWithZero()
715 Sd(zero_reg, MemOperand(a0)); in FillStackSlotsWithZero()
744 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_divs()
753 Operand(zero_reg)); in emit_i32_divs()
760 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_divu()
766 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_rems()
772 TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); in emit_i32_remu()
848 TurboAssembler::Branch(trap_div_by_zero, eq, rhs.gp(), Operand(zero_reg)); in emit_i64_divs()
858 Operand(zero_reg)); in emit_i64_divs()
[all …]
/external/v8/src/wasm/baseline/x64/
Dliftoff-assembler-x64.h1746 DoubleRegister zero_reg = kScratchDoubleReg; in EmitSatTruncateFloatToInt() local
1771 __ xorpd(zero_reg, zero_reg); in EmitSatTruncateFloatToInt()
1775 __ Ucomisd(src, zero_reg); in EmitSatTruncateFloatToInt()
1777 __ Ucomiss(src, zero_reg); in EmitSatTruncateFloatToInt()
1821 DoubleRegister zero_reg = kScratchDoubleReg; in EmitSatTruncateFloatToUInt64() local
1823 __ xorpd(zero_reg, zero_reg); in EmitSatTruncateFloatToUInt64()
1825 __ Ucomisd(src, zero_reg); in EmitSatTruncateFloatToUInt64()
1827 __ Ucomiss(src, zero_reg); in EmitSatTruncateFloatToUInt64()
1840 __ movq(dst, zero_reg); in EmitSatTruncateFloatToUInt64()
/external/v8/src/execution/mips/
Dsimulator-mips.h116 zero_reg = 0, enumerator
/external/v8/src/execution/mips64/
Dsimulator-mips64.h116 zero_reg = 0, enumerator
/external/v8/src/wasm/baseline/ia32/
Dliftoff-assembler-ia32.h2160 DoubleRegister zero_reg = in EmitSatTruncateFloatToInt() local
2186 __ Xorpd(zero_reg, zero_reg); in EmitSatTruncateFloatToInt()
2190 __ ucomisd(src, zero_reg); in EmitSatTruncateFloatToInt()
2192 __ ucomiss(src, zero_reg); in EmitSatTruncateFloatToInt()

12