| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 87 unsigned &IndexReg, in findSRegBaseAndIndex()
176 unsigned IndexReg = 0; in fixupGlobalSaddr() local
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand() local
207 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
226 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand() local
357 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in emitMemModRMByte() local
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference() local
298 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference() local
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| D | X86InstrBuilder.h | 49 unsigned IndexReg; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 286 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
352 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
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| D | X86FixupLEAs.cpp | 369 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
549 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
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| D | X86InsertPrefetch.cpp | 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| D | X86InstrBuilder.h | 54 unsigned IndexReg; member
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| /external/llvm-project/llvm/tools/llvm-exegesis/lib/X86/ |
| D | Target.cpp | 254 for (const unsigned IndexReg : PossibleIndexRegs.set_bits()) { in generateLEATemplatesCommon() local
318 BitVector &CandidateDestRegs) { in generateCodeTemplates()
378 BitVector &CandidateDestRegs) { in generateCodeTemplates()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 289 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
355 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
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| D | X86FixupLEAs.cpp | 385 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
570 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
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| D | X86InsertPrefetch.cpp | 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| D | X86InstrBuilder.h | 54 unsigned IndexReg; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 187 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand() local
206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() local
228 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand() local
377 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
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| D | X86ATTInstPrinter.cpp | 389 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
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| D | X86IntelInstPrinter.cpp | 348 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
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| D | X86MCTargetDesc.cpp | 532 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
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| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 166 unsigned IndexReg = Index.getReg(); in is16BitMemOperand() local
183 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() local
205 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand() local
387 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
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| D | X86ATTInstPrinter.cpp | 399 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
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| D | X86IntelInstPrinter.cpp | 357 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 198 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
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| D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anond14900950111::X86AsmParser::IntelExprStateMachine
831 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexReg()
1160 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm()
1440 int IndexReg = SM.getIndexReg(); in ParseIntelBracExpression() local
2054 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon7e5fbfb70111::X86AsmParser::IntelExprStateMachine
1043 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexRegAndScale()
1409 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm()
1971 unsigned IndexReg = SM.getIndexReg(); in ParseIntelOperand() local
2294 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 433 unsigned &IndexReg) { in PPCSimplifyAddress()
519 unsigned IndexReg = 0; in PPCEmitLoad() local
655 unsigned IndexReg = 0; in PPCEmitStore() local
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