| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy()
245 unsigned SubReg; in isProfitableToTransform() local
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy()
245 unsigned SubReg; in isProfitableToTransform() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 112 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
121 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
137 unsigned &SubReg) { in getSrcFromCopy()
253 unsigned SubReg; in isProfitableToTransform() local
|
| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
340 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
371 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
453 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
475 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
493 unsigned SubReg = *SubRegs; in UpdatePhysRegDefs() local
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| D | DetectDeadLanes.cpp | 180 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
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| D | LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); in calculate() local
175 unsigned SubReg = MO.getSubReg(); in extendToUses() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
340 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
371 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
453 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
475 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
493 unsigned SubReg = *SubRegs; in UpdatePhysRegDefs() local
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| D | DetectDeadLanes.cpp | 177 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
427 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
460 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
340 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
371 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
453 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
475 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
493 unsigned SubReg = *SubRegs; in UpdatePhysRegDefs() local
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| D | LiveIntervalCalc.cpp | 68 unsigned SubReg = MO.getSubReg(); in calculate() local
168 unsigned SubReg = MO.getSubReg(); in extendToUses() local
|
| D | DetectDeadLanes.cpp | 174 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
424 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
457 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 81 unsigned SubReg; member in __anondebd7f180111::GCNRegBankReassign::OperandMask
102 unsigned SubReg; member in __anondebd7f180111::GCNRegBankReassign::Candidate
255 Printable printReg(Register Reg, unsigned SubReg = 0) const { in printReg()
329 uint32_t GCNRegBankReassign::getRegBankMask(Register Reg, unsigned SubReg, in getRegBankMask()
393 unsigned SubReg, int Bank) { in analyzeInst()
553 unsigned SubReg, in getFreeBanks()
632 unsigned SubReg, int Bank, in computeStallCycles()
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| D | SIRegisterInfo.h | 310 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg()
315 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg()
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| D | SIShrinkInstructions.cpp | 396 Register Reg, unsigned SubReg, in instAccessReg()
416 unsigned Reg, unsigned SubReg, in instReadsReg()
422 unsigned Reg, unsigned SubReg, in instModifiesReg()
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| D | SIPreAllocateWWMRegs.cpp | 135 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
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| D | SIFormMemoryClauses.cpp | 376 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction()
385 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction()
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| D | SIAddIMGInit.cpp | 148 Register SubReg = in runOnMachineFunction() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
|
| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 533 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
540 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
545 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
559 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 528 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
535 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
540 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
554 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 80 unsigned SubReg; member in __anon8074828c0111::GCNRegBankReassign::OperandMask
232 Printable printReg(unsigned Reg, unsigned SubReg = 0) const { in printReg()
295 unsigned GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, in getRegBankMask()
491 unsigned SubReg, in getFreeBanks()
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| D | SIShrinkInstructions.cpp | 390 unsigned Reg, unsigned SubReg, in instAccessReg()
411 unsigned Reg, unsigned SubReg, in instReadsReg()
417 unsigned Reg, unsigned SubReg, in instModifiesReg()
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| D | SIPreAllocateWWMRegs.cpp | 136 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
|
| D | SIFormMemoryClauses.cpp | 376 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction()
385 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction()
|