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/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvec_conv_fp64_to_i32_elts.ll66 ; CHECK-P8-NEXT: xxmrgld vs2, vs0, vs1
68 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs2
77 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
79 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs2
88 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
90 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs2
109 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
113 ; CHECK-P8-NEXT: xxswapd vs2, vs2
116 ; CHECK-P8-NEXT: xxmrgld vs1, vs2, vs3
117 ; CHECK-P8-NEXT: xxmrghd vs2, vs2, vs3
[all …]
Dvec_conv_fp32_to_i64_elts.ll97 ; CHECK-P8-NEXT: xxmrglw vs2, v3, v3
101 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
105 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs2
112 ; CHECK-P8-NEXT: xxswapd vs2, v5
115 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
123 ; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1
127 ; CHECK-P9-NEXT: xvcvspdp vs2, vs2
131 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
138 ; CHECK-P9-NEXT: stxv vs2, 0(r3)
145 ; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1
[all …]
Dvec_conv_i32_to_fp64_elts.ll92 ; CHECK-P8-NEXT: xvcvuxwdp vs2, v5
96 ; CHECK-P8-NEXT: xxswapd vs2, vs2
103 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
111 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
117 ; CHECK-P9-NEXT: stxv vs2, 0(r3)
129 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
135 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
168 ; CHECK-P8-NEXT: xvcvuxwdp vs2, v2
178 ; CHECK-P8-NEXT: xxswapd vs2, vs2
190 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
[all …]
Dvec_conv_fp_to_i_8byte_elts.ll79 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
83 ; CHECK-P8-NEXT: xvcvdpuxds vs2, vs2
84 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
94 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
97 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
102 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
110 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
113 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
118 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
140 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
[all …]
Dmma-outer-product.ll23 ; CHECK-NEXT: xxlor vs2, v4, v4
33 ; CHECK-NEXT: stxv vs2, 16(r3)
48 ; CHECK-BE-NEXT: xxlor vs2, v4, v4
59 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
83 ; CHECK-NEXT: xxlor vs2, vs6, vs6
93 ; CHECK-NEXT: stxv vs2, 0(r4)
107 ; CHECK-BE-NEXT: xxlor vs2, vs6, vs6
118 ; CHECK-BE-NEXT: stxv vs2, 0(r5)
151 ; CHECK-NEXT: stxv vs2, 16(r7)
162 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
[all …]
Dbfloat16-outer-product.ll17 ; CHECK-NEXT: stxv vs2, 16(r7)
28 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
48 ; CHECK-NEXT: stxv vs2, 16(r7)
59 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
78 ; CHECK-NEXT: lxv vs2, 16(r3)
84 ; CHECK-NEXT: stxv vs2, 16(r7)
93 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
100 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
121 ; CHECK-NEXT: lxv vs2, 16(r3)
127 ; CHECK-NEXT: stxv vs2, 16(r7)
[all …]
Dvec_conv_i_to_fp_8byte_elts.ll79 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
83 ; CHECK-P8-NEXT: xvcvuxddp vs2, vs2
84 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
98 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
101 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
114 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
117 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
140 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
148 ; CHECK-P8-NEXT: xvcvuxddp vs2, vs2
157 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
[all …]
Dmma-integer-based-outer-product.ll17 ; CHECK-NEXT: stxv vs2, 16(r7)
28 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
48 ; CHECK-NEXT: stxv vs2, 16(r7)
59 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
78 ; CHECK-NEXT: lxv vs2, 16(r3)
84 ; CHECK-NEXT: stxv vs2, 16(r7)
93 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
100 ; CHECK-BE-NEXT: stxv vs2, 32(r7)
121 ; CHECK-NEXT: lxv vs2, 16(r3)
127 ; CHECK-NEXT: stxv vs2, 16(r7)
[all …]
Dvec_conv_fp32_to_i8_elts.ll86 ; CHECK-P8-NEXT: xxswapd vs2, v2
89 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
234 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
235 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
238 ; CHECK-P9-NEXT: xxswapd vs2, vs1
240 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
286 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
287 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
290 ; CHECK-BE-NEXT: xxswapd vs2, vs1
292 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
[all …]
Dvec_conv_fp32_to_i16_elts.ll79 ; CHECK-P8-NEXT: xxswapd vs2, v2
82 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
223 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
224 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
227 ; CHECK-P9-NEXT: xxswapd vs2, vs1
229 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
274 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
275 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
278 ; CHECK-BE-NEXT: xxswapd vs2, vs1
280 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
[all …]
Dmma-intrinsics.ll17 ; CHECK-NEXT: xxlor vs2, v2, v2
21 ; CHECK-NEXT: stxv vs2, 16(r3)
30 ; CHECK-BE-NEXT: xxlor vs2, v2, v2
35 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
73 ; CHECK-NEXT: xxlor vs2, v2, v2
78 ; CHECK-NEXT: stxv vs2, 16(r3)
87 ; CHECK-BE-NEXT: xxlor vs2, v2, v2
93 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
112 ; CHECK-NEXT: xxlor vs2, v2, v2
116 ; CHECK-NEXT: stxv vs2, 16(r3)
[all …]
Dvec_conv_i_to_fp_4byte_elts.ll125 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
128 ; CHECK-P9-NEXT: xvcvuxwsp vs2, vs2
133 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
141 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
144 ; CHECK-BE-NEXT: xvcvuxwsp vs2, vs2
149 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
272 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
275 ; CHECK-P9-NEXT: xvcvsxwsp vs2, vs2
280 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
288 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
[all …]
Dvec_conv_fp_to_i_4byte_elts.ll125 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
128 ; CHECK-P9-NEXT: xvcvspuxws vs2, vs2
133 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
141 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
144 ; CHECK-BE-NEXT: xvcvspuxws vs2, vs2
149 ; CHECK-BE-NEXT: stxv vs2, 16(r3)
272 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
275 ; CHECK-P9-NEXT: xvcvspsxws vs2, vs2
280 ; CHECK-P9-NEXT: stxv vs2, 16(r3)
288 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
[all …]
Dvec_conv_fp64_to_i16_elts.ll154 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
162 ; CHECK-P8-NEXT: xxswapd vs2, vs2
197 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
207 ; CHECK-P9-NEXT: xxswapd vs2, vs2
240 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
251 ; CHECK-BE-NEXT: xxswapd vs2, vs2
301 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
315 ; CHECK-P8-NEXT: xxswapd vs2, vs2
388 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
396 ; CHECK-P9-NEXT: xxswapd vs2, vs2
[all …]
Dvec_conv_i16_to_fp64_elts.ll139 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0
143 ; CHECK-P8-NEXT: xxswapd vs2, vs2
145 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
173 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
176 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
202 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
205 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
246 ; CHECK-P8-NEXT: xvcvuxddp vs2, v5
254 ; CHECK-P8-NEXT: xxswapd vs2, vs2
259 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
[all …]
Dmma-acc-memops.ll18 ; LE-PAIRED-NEXT: plxv vs2, f@PCREL+80(0), 1
21 ; LE-PAIRED-NEXT: pstxv vs2, f@PCREL+144(0), 1
32 ; BE-PAIRED-NEXT: lxv vs2, 96(r3)
36 ; BE-PAIRED-NEXT: stxv vs2, 160(r3)
55 ; LE-PAIRED-NEXT: lxv vs2, 16(r6)
61 ; LE-PAIRED-NEXT: stxv vs2, 16(r3)
74 ; BE-PAIRED-NEXT: lxv vs2, 32(r6)
79 ; BE-PAIRED-NEXT: stxv vs2, 32(r3)
95 ; LE-PAIRED-NEXT: plxv vs2, f@PCREL+27(0), 1
98 ; LE-PAIRED-NEXT: pstxv vs2, f@PCREL+35(0), 1
[all …]
Dvec_conv_i8_to_fp64_elts.ll138 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0
142 ; CHECK-P8-NEXT: xxswapd vs2, vs2
146 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
175 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
178 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
205 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
208 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
259 ; CHECK-P8-NEXT: xvcvuxddp vs2, v6
267 ; CHECK-P8-NEXT: xxswapd vs2, vs2
272 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
[all …]
Dvec_conv_i64_to_fp32_elts.ll110 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
114 ; CHECK-P8-NEXT: xxswapd v4, vs2
118 ; CHECK-P8-NEXT: xvcvuxdsp vs2, v4
122 ; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3
184 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
194 ; CHECK-P8-NEXT: xxswapd v4, vs2
195 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
202 ; CHECK-P8-NEXT: xxswapd v4, vs2
203 ; CHECK-P8-NEXT: xvcvuxdsp vs2, v5
212 ; CHECK-P8-NEXT: xxsldwi v5, vs2, vs2, 3
[all …]
Dvec_conv_fp64_to_i8_elts.ll163 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
171 ; CHECK-P8-NEXT: xxswapd vs2, vs2
208 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
218 ; CHECK-P9-NEXT: xxswapd vs2, vs2
252 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
263 ; CHECK-BE-NEXT: xxswapd vs2, vs2
314 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
327 ; CHECK-P8-NEXT: xxswapd vs2, vs2
406 ; CHECK-P9-NEXT: lxv vs2, 80(r3)
450 ; CHECK-P9-NEXT: xxswapd vs2, vs2
[all …]
Dprefer-dqform.ll16 ; CHECK-P9: lxv vs2, 0(r4)
21 ; CHECK-P9-DAG: xvmaddadp vs2, vs4, vs0
22 ; CHECK-P9: stxv vs2, 0(r4)
29 ; CHECK-P10: lxv vs2, 0(r4)
33 ; CHECK-P10-DAG: xvmaddadp vs2, vs4, vs0
35 ; CHECK-P10: stxv vs2, 0(r4)
/external/rust/crates/libz-sys/src/zlib-ng/arch/power/
Dadler32_power8.c79 vector unsigned int vs2 = { 0 }; in adler32_power8() local
86 vs2[0] = s2; in adler32_power8()
101 vs2 = vec_add(vsum2, vs2); in adler32_power8()
108 vs2 = vec_add(vs1_save, vs2); in adler32_power8()
109 vs2 = vec_sumsu(vs2, vsum2); in adler32_power8()
113 /* vs2[0] = s2_i + 16*s1_save + in adler32_power8()
115 vs2[0] = vs2[0] % BASE; in adler32_power8()
118 vs2 = vec_and(vs2, vmask); in adler32_power8()
136 vs2 = vec_add(vsum2, vs2); in adler32_power8()
143 vs2 = vec_add(vs1_save, vs2); in adler32_power8()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoV.td100 // load vd, (rs1), vs2, vm
104 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
105 "$vd, (${rs1}), $vs2$vm">;
130 // segment load vd, (rs1), vs2, vm
134 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
135 "$vd, (${rs1}), $vs2$vm">;
152 // store vd, vs3, (rs1), vs2, vm
155 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
156 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
179 // segment store vd, vs3, (rs1), vs2, vm
[all …]
DRISCVInstrFormatsV.td106 bits<5> vs2;
113 let Inst{24-20} = vs2;
126 bits<5> vs2;
133 let Inst{24-20} = vs2;
143 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
152 let Inst{24-20} = vs2;
165 bits<5> vs2;
172 let Inst{24-20} = vs2;
185 bits<5> vs2;
191 let Inst{24-20} = vs2;
[all …]
/external/rust/crates/libz-sys/src/zlib-ng/arch/x86/
Dadler32_ssse3.c56 __m128i vs2 = _mm_load_si128((__m128i*)s2); in adler32_ssse3() local
66 vs2 = sum2 + 16 vs1 + sum( (16-i+1) c[i] ) in adler32_ssse3()
83 vsum2 = _mm_add_epi32(vsum2, vs2); in adler32_ssse3()
84 vs2 = _mm_add_epi32(vsum2, vs1_0); in adler32_ssse3()
88 … // At this point, we have partial sums stored in vs1 and vs2. There are AVX512 instructions that in adler32_ssse3()
95 _mm_store_si128((__m128i*)s2_unpack, vs2); in adler32_ssse3()
Dadler32_avx.c59 __m256i vs2 = _mm256_load_si256((__m256i*)s2); in adler32_avx2() local
69 vs2 = sum2 + 16 vs1 + sum( (16-i+1) c[i] ) in adler32_avx2()
81 vsum2 = _mm256_add_epi32(vsum2, vs2); in adler32_avx2()
82 vs2 = _mm256_add_epi32(vsum2, vs1_0); in adler32_avx2()
86 … // At this point, we have partial sums stored in vs1 and vs2. There are AVX512 instructions that in adler32_avx2()
92 _mm256_store_si256((__m256i*)s2_unpack, vs2); in adler32_avx2()

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