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Searched refs:AddrBaseReg (Results 1 – 25 of 44) sorted by relevance

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/external/llvm-project/llvm/lib/Target/X86/
DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
217 assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
DX86OptimizeLEAs.cpp194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
460 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
466 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
561 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
DX86AsmPrinter.cpp288 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
325 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
353 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
375 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
DX86FixupLEAs.cpp372 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
467 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
504 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
556 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
DX86CallFrameOptimization.cpp427 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
217 assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
DX86OptimizeLEAs.cpp194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
460 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
466 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
561 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
DX86AsmPrinter.cpp285 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
322 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
350 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
372 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
DX86FixupLEAs.cpp357 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
450 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
486 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
536 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
DX86CallFrameOptimization.cpp427 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp174 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
330 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
424 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
430 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
520 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
DX86AsmPrinter.cpp231 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference()
267 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier); in printLeaMemReference()
296 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference()
312 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier, AsmVariant); in printIntelMemReference()
DX86FixupLEAs.cpp254 unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg(); in isLEASimpleIncOrDec()
307 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
DX86CallFrameOptimization.cpp385 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
386 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
DX86InstrInfo.h125 MI.getOperand(Op + X86::AddrBaseReg).isReg() && in isLeaMem()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand()
375 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
879 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
925 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
941 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
958 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
985 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1210 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in determineREXPrefix()
[all …]
DX86ATTInstPrinter.cpp388 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
409 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
DX86IntelInstPrinter.cpp346 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
358 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp162 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
182 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
204 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand()
385 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
901 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
948 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
964 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
981 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1008 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1247 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in emitREXPrefix()
[all …]
DX86ATTInstPrinter.cpp398 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
419 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
DX86IntelInstPrinter.cpp355 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
367 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand()
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand()
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand()
355 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); in emitMemModRMByte()
720 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in EmitVEXOpcodePrefix()
766 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in EmitVEXOpcodePrefix()
798 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in EmitVEXOpcodePrefix()
996 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B in DetermineREXPrefix()
1006 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B in DetermineREXPrefix()
1016 REX |= isX86_64ExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B in DetermineREXPrefix()
DX86BaseInfo.h33 AddrBaseReg = 0, enumerator
/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
175 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
DX86ATTInstPrinter.cpp197 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
222 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()

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