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Searched refs:BIT_32 (Results 1 – 21 of 21) sorted by relevance

/external/arm-trusted-firmware/include/drivers/arm/
Dgicv3.h128 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
129 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
130 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
131 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
132 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
133 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
134 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
195 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
198 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
199 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
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Dgicv2.h71 #define EOI_MODE_NS BIT_32(10)
72 #define EOI_MODE_S BIT_32(9)
73 #define IRQ_BYP_DIS_GRP1 BIT_32(8)
74 #define FIQ_BYP_DIS_GRP1 BIT_32(7)
75 #define IRQ_BYP_DIS_GRP0 BIT_32(6)
76 #define FIQ_BYP_DIS_GRP0 BIT_32(5)
77 #define CBPR BIT_32(4)
79 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
80 #define ACK_CTL BIT_32(2)
114 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
Dcci.h70 #define DVM_EN_BIT BIT_32(1)
71 #define SNOOP_EN_BIT BIT_32(0)
72 #define SUPPORT_SNOOPS BIT_32(30)
73 #define SUPPORT_DVM BIT_32(31)
76 #define CHANGE_PENDING_BIT BIT_32(0)
Dtzc380.h45 #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
46 #define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
60 #define TZC_SP_NS_W BIT_32(0)
61 #define TZC_SP_NS_R BIT_32(1)
62 #define TZC_SP_S_W BIT_32(2)
63 #define TZC_SP_S_R BIT_32(3)
Dtzc400.h47 #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
48 #define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
Dgic_common.h62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
/external/arm-trusted-firmware/include/drivers/arm/fvp/
Dfvp_pwrc.h17 #define PWKUPR_WEN BIT_32(31)
19 #define PSYSR_AFF_L2 BIT_32(31)
20 #define PSYSR_AFF_L1 BIT_32(30)
21 #define PSYSR_AFF_L0 BIT_32(29)
22 #define PSYSR_WEN BIT_32(28)
23 #define PSYSR_PC BIT_32(27)
24 #define PSYSR_PP BIT_32(26)
/external/arm-trusted-firmware/services/std_svc/sdei/
Dsdei_private.h100 return ((map->map_flags & BIT_32(SDEI_MAPF_PRIVATE_SHIFT_)) != 0U); in is_event_private()
110 return ((map->map_flags & BIT_32(SDEI_MAPF_CRITICAL_SHIFT_)) != 0U); in is_event_critical()
120 return ((map->map_flags & BIT_32(SDEI_MAPF_SIGNALABLE_SHIFT_)) != 0U); in is_event_signalable()
125 return ((map->map_flags & BIT_32(SDEI_MAPF_DYNAMIC_SHIFT_)) != 0U); in is_map_dynamic()
136 return ((map->map_flags & BIT_32(SDEI_MAPF_BOUND_SHIFT_)) != 0U); in is_map_bound()
141 map->map_flags |= BIT_32(SDEI_MAPF_BOUND_SHIFT_); in set_map_bound()
146 return ((map->map_flags & BIT_32(SDEI_MAPF_EXPLICIT_SHIFT_)) != 0U); in is_map_explicit()
151 map->map_flags &= ~BIT_32(SDEI_MAPF_BOUND_SHIFT_); in clr_map_bound()
181 return ((se->state & BIT_32(bit_no)) != 0U); in get_ev_state_bit()
186 se->state &= ~BIT_32(bit_no); in clr_ev_state_bit()
/external/arm-trusted-firmware/include/plat/arm/board/common/
Dv2m_def.h23 #define V2M_CFGCTRL_START BIT_32(31)
24 #define V2M_CFGCTRL_RW BIT_32(30)
96 #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
97 #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
98 #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
99 #define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
/external/arm-trusted-firmware/plat/allwinner/sun50i_a64/
Dsunxi_power.c45 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
52 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
60 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc()
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc()
/external/arm-trusted-firmware/plat/arm/board/fvp/
Dfvp_def.h122 #define FVP_SP810_CTRL_TIM0_OV BIT_32(16)
123 #define FVP_SP810_CTRL_TIM1_OV BIT_32(18)
124 #define FVP_SP810_CTRL_TIM2_OV BIT_32(20)
125 #define FVP_SP810_CTRL_TIM3_OV BIT_32(22)
/external/arm-trusted-firmware/drivers/arm/gic/v3/
Dgic600_multichip_private.h22 #define GICD_DCHIPR_PUP_BIT BIT_32(0)
23 #define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5))
Dgicv3_main.c1157 tgt = BIT_32(aff0); in gicv3_raise_secure_g0_sgi()
/external/icing/icing/portable/
Dplatform.h63 BIT_32, enumerator
73 return BIT_32; in GetArchitecture()
/external/deqp/external/vulkancts/modules/vulkan/shaderexecutor/
DvktShaderClockTests.cpp76 BIT_32 = 0, enumerator
244 {SUBGROUP, BIT_32, "clock2x32ARB" }, in addShaderClockTests()
246 {DEVICE, BIT_32, "clockRealtime2x32EXT"} in addShaderClockTests()
/external/arm-trusted-firmware/include/lib/
Dutils_def.h22 #define BIT_32(nr) (U(1) << (nr)) macro
28 #define BIT BIT_32
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_cpu_ops.c81 BIT_32(core)); in sunxi_cpu_off()
/external/arm-trusted-firmware/drivers/mmc/
Dmmc.c273 mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len); in mmc_fill_device_info()
/external/arm-trusted-firmware/include/arch/aarch32/
Darch.h310 #define SPSR_SSBS_BIT BIT_32(23)
/external/icing/icing/file/
Dfile-backed-proto-log.h664 case Architecture::BIT_32: in ComputeChecksum()
Dportable-file-backed-proto-log.h836 case Architecture::BIT_32: in ComputeChecksum()