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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fcmp.mir14 ; GFX7: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[COPY]]
15 ; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
20 ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[COPY]]
21 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
26 ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[COPY]]
27 ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
44 ; GFX7: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s64), [[COPY]]
45 ; GFX7: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
50 ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s64), [[COPY]]
51 ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
[all …]
Dlegalize-intrinsic-amdgcn-fdiv-fast.mir17 ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
18 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
43 ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
44 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
Dlegalize-intrinsic-round.mir23 ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
24 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
38 ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
39 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
53 ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
54 ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
79 ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
80 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[OR]], [[C]]
94 ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
95 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[OR]], [[C]]
[all …]
Dregbankselect-fcmp.mir16 ; CHECK: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY2]]
32 ; CHECK: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]]
49 ; CHECK: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY1]](s32), [[COPY2]]
Dinst-select-fcmp.mir16 ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
17 ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
21 ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
22 ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
376 ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
377 ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
381 ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
382 ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
400 ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
401 ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
[all …]
Dinst-select-fcmp.s16.mir18 ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
19 ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
25 ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
26 ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
411 ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
412 ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
418 ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
419 ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
Dlegalize-frint.mir68 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
69 ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FADD1]]
140 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
141 ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FADD1]]
Dlegalize-fceil.mir101 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
103 ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
218 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]]
220 ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
Dlegalize-fptoui.mir197 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
198 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
316 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
317 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
442 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[COPY]](s32), [[C9]]
443 ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[SELECT1]], [[XOR2]]
506 ; VI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[COPY]](s32), [[C9]]
507 ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[SELECT1]], [[XOR2]]
582 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[UV]](s32), [[C9]]
583 ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[SELECT1]], [[XOR2]]
[all …]
Dlegalize-ffloor.mir40 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY]]
41 ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
98 ; SI: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ord), [[COPY]](s64), [[COPY]]
99 ; SI: [[SELECT:%[0-9]+]]:_(s64) = nsz G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
229 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[UV]](s64), [[UV]]
230 ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FMINNUM_IEEE]]
Dlegalize-fptosi.mir197 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
198 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
316 ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
317 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Dfcmp.mir23 ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
24 ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
31 ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
32 ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
56 ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
57 ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
64 ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
65 ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dfcmp.mir22 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
23 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
30 ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
31 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
54 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
55 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
62 ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
63 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
Dfptosi_and_fptoui.mir353 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
355 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
369 ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
371 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
399 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
401 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
418 ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
420 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
452 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
454 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
Dx86_64-legalize-fcmp.mir168 ; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(oeq), [[TRUNC]](s32), [[TRUNC1]]
169 ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
203 ; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ogt), [[TRUNC]](s32), [[TRUNC1]]
204 ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
238 ; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(oge), [[TRUNC]](s32), [[TRUNC1]]
239 ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
273 ; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(olt), [[TRUNC]](s32), [[TRUNC1]]
274 ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
308 ; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ole), [[TRUNC]](s32), [[TRUNC1]]
309 ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
[all …]
Dregbankselect-X86_64.mir2532 ; FAST: [[FCMP:%[0-9]+]]:gpr(s8) = G_FCMP floatpred(oeq), [[TRUNC]](s32), [[TRUNC1]]
2533 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2542 ; GREEDY: [[FCMP:%[0-9]+]]:gpr(s8) = G_FCMP floatpred(oeq), [[TRUNC]](s32), [[TRUNC1]]
2543 ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2579 ; FAST: [[FCMP:%[0-9]+]]:gpr(s8) = G_FCMP floatpred(ogt), [[TRUNC]](s32), [[TRUNC1]]
2580 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2589 ; GREEDY: [[FCMP:%[0-9]+]]:gpr(s8) = G_FCMP floatpred(ogt), [[TRUNC]](s32), [[TRUNC1]]
2590 ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2626 ; FAST: [[FCMP:%[0-9]+]]:gpr(s8) = G_FCMP floatpred(oge), [[TRUNC]](s32), [[TRUNC1]]
2627 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-fcmp.mir12 ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]]
13 ; CHECK: $w0 = COPY [[FCMP]](s32)
Dretry-artifact-combine.mir10 ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]]
12 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
Dregbank-fp-use-def.mir28 ; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[C]](s32), [[LOAD]]
29 ; CHECK: $w0 = COPY [[FCMP]](s32)
51 ; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[UV]](s32), [[UV1]]
52 ; CHECK: $w0 = COPY [[FCMP]](s32)
Dprelegalizercombiner-invert-cmp.mir43 ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](s64), [[C]]
44 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
/external/llvm/test/Transforms/InstCombine/
Dpow-1.ll76 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq float %x, 0xFFF0000000000000
77 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], float 0x7FF0000000000000, float [[FABSF]]
87 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq double %x, 0xFFF0000000000000
88 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
167 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq double %x, 0xFFF0000000000000
168 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
D2008-11-08-FCmp.ll4 ; When inst combining an FCMP with the LHS coming from a uitofp instruction, we
/external/llvm-project/llvm/test/Transforms/InstCombine/
D2008-11-08-FCmp.ll4 ; When inst combining an FCMP with the LHS coming from a uitofp instruction, we
/external/llvm-project/llvm/test/Bitcode/
Dinvalid.test235 RUN: FileCheck --check-prefix=INVALID-FCMP-OPNUM %s
237 INVALID-FCMP-OPNUM: Invalid record: operand number exceeded available operands
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.h61 FCMP, enumerator

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