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Searched refs:IR3_REG_HALF (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/freedreno/ir3/
Dir3_validate.c59 return reg->flags & (IR3_REG_HALF | IR3_REG_HIGH); in reg_class_flags()
102 validate_assert(ctx, !(reg->flags & IR3_REG_HALF)); in validate_instr()
104 validate_assert(ctx, reg->flags & IR3_REG_HALF); in validate_instr()
107 validate_assert(ctx, (last_reg->flags & IR3_REG_HALF) == (reg->flags & IR3_REG_HALF)); in validate_instr()
121 if (instr->regs[0]->flags & IR3_REG_HALF) { in validate_instr()
126 if (instr->regs[1]->flags & IR3_REG_HALF) { in validate_instr()
136 if (instr->regs[1]->flags & IR3_REG_HALF) { in validate_instr()
144 if (instr->regs[0]->flags & IR3_REG_HALF) { in validate_instr()
151 if (instr->regs[0]->flags & IR3_REG_HALF) { in validate_instr()
Dir3.c75 iassert(!((reg)->flags & IR3_REG_HALF)); \
77 iassert((reg)->flags & IR3_REG_HALF); \
116 if (reg->flags & IR3_REG_HALF) { in reg()
175 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV); in emit_cat1()
180 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF); in emit_cat1()
186 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF); in emit_cat1()
230 IR3_REG_HALF | absneg); in emit_cat2()
236 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | in emit_cat2()
242 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF | in emit_cat2()
251 !((src1->flags ^ src2->flags) & IR3_REG_HALF)); in emit_cat2()
[all …]
Dir3.h77 IR3_REG_HALF = 0x004, enumerator
665 unsigned type_reg1 = (reg1->flags & (IR3_REG_HIGH | IR3_REG_HALF)); in is_same_type_reg()
666 unsigned type_reg2 = (reg2->flags & (IR3_REG_HIGH | IR3_REG_HALF)); in is_same_type_reg()
772 return !!(instr->regs[0]->flags & IR3_REG_HALF); in is_half()
1357 if (src->regs[0]->flags & IR3_REG_HALF) in __ssa_src()
1358 flags |= IR3_REG_HALF; in __ssa_src()
1376 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; in create_immed_typed()
1397 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; in create_uniform_typed()
1435 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; in ir3_MOV()
1455 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0; in ir3_COV()
[all …]
Dir3_cf.c80 use->regs[1]->flags |= IR3_REG_HALF; in rewrite_src_uses()
82 use->regs[1]->flags &= ~IR3_REG_HALF; in rewrite_src_uses()
Dir3_context.c263 dst->regs[1]->flags |= IR3_REG_HALF; in ir3_put_dst()
296 return instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH); in dest_flags()
341 type_t type = (flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32; in ir3_create_collect()
456 instr->regs[0]->flags |= IR3_REG_HALF; in create_addr0()
591 flags |= IR3_REG_HALF; in ir3_create_array_load()
652 flags |= IR3_REG_HALF; in ir3_create_array_store()
Dir3_group.c38 (collect->regs[idx+1]->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32); in insert_mov()
Dir3_parser.y142 flags |= IR3_REG_HALF; in new_reg()
830 | T_A0 { $$ = new_reg((61 << 3) + $1, IR3_REG_HALF); }
877 | T_HR '<' T_A0 offset '>' { new_reg(0, IR3_REG_RELATIV | IR3_REG_HALF)->array.of…
878 …C '<' T_A0 offset '>' { new_reg(0, IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_HALF)->array.offset …
Dir3_postsched.c386 if (reg->flags & IR3_REG_HALF) { in add_reg_dep()
395 if (reg->flags & IR3_REG_HALF) in add_reg_dep()
Dir3_shader.c547 (reg->flags & IR3_REG_HALF) ? "h" : "", in ir3_shader_disasm()
569 (reg->flags & IR3_REG_HALF) ? "h" : "", in ir3_shader_disasm()
Dir3_print.c178 if (reg->flags & IR3_REG_HALF) in print_reg_name()
Dir3_compiler_nir.c665 hi->regs[0]->flags |= IR3_REG_HALF; in emit_alu()
666 lo->regs[0]->flags |= IR3_REG_HALF; in emit_alu()
669 dst[0]->regs[0]->flags |= IR3_REG_HALF; in emit_alu()
1823 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF; in emit_intrinsic()
1844 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF; in emit_intrinsic()
3484 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF); in collect_tex_prefetches()
3770 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF); in ir3_compile_shader_nir()
3781 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) == in ir3_compile_shader_nir()
3788 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF); in ir3_compile_shader_nir()
Dir3_cp.c171 if (f_opcode && (new_flags & IR3_REG_HALF)) in lower_immed()
Dir3_ra.c1179 reg->flags |= IR3_REG_HALF; in reg_assign()
1360 ra_assert(ctx, !(instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH))); in ra_precolor()
/external/mesa3d/src/freedreno/ir3/tests/
Ddelay.c104 if (reg->flags & IR3_REG_HALF) in regn()
136 unsigned flags = src->regs[0]->flags & IR3_REG_HALF; in regs_to_ssa()
154 unsigned flags = instr->regs[0]->flags & IR3_REG_HALF; in regs_to_ssa()
/external/mesa3d/docs/relnotes/
D20.1.0.rst2742 - freedreno/ir3: Set IR3_REG_HALF flag on src as well in immediate MOV
D20.2.0.rst1648 - freedreno/ir3: Drop redundant IR3_REG_HALF setup in ALU ops.