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Searched refs:InVec (Results 1 – 25 of 32) sorted by relevance

12

/external/llvm/test/Transforms/InstCombine/
Dvector-mul.ll6 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
8 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
15 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
17 %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
22 ; CHECK: ret <4 x i8> %InVec
24 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
26 %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
31 ; CHECK: shl <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
34 define <4 x i8> @SplatPow2Test1_i8(<4 x i8> %InVec) {
36 %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
[all …]
Dx86-pshufb.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
8 ; CHECK-NEXT: ret <16 x i8> %InVec
10 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
14 define <32 x i8> @identity_test_avx2(<32 x i8> %InVec) {
16 ; CHECK-NEXT: ret <32 x i8> %InVec
18 …%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 …
24 define <16 x i8> @fold_to_zero_vector(<16 x i8> %InVec) {
28 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
32 define <32 x i8> @fold_to_zero_vector_avx2(<32 x i8> %InVec) {
36 …%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 -128, i8 …
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dvector-mul.ll7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
23 %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
34 %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
38 define <4 x i8> @SplatPow2Test1_i8(<4 x i8> %InVec) {
45 %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
49 define <4 x i8> @SplatPow2Test2_i8(<4 x i8> %InVec) {
56 %mul = mul <4 x i8> %InVec, <i8 8, i8 8, i8 8, i8 8>
[all …]
/external/llvm/test/CodeGen/X86/
Dsse2-vector-shifts.ll6 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
11 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
21 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
31 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
40 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
44 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
50 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
[all …]
Davx2-vector-shifts.ll6 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
11 …%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 …
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
21 …%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
31 …%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16…
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
40 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
44 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
50 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dsse2-vector-shifts.ll8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
13 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
23 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
33 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
42 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
52 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
[all …]
Davx2-vector-shifts.ll9 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
18 …%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 …
22 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
33 …%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
37 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
48 …%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16…
52 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
61 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
65 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
76 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
[all …]
Dcombine-mul.ll396 define <4 x i64> @fuzz15429(<4 x i64> %InVec) {
415 %mul = mul <4 x i64> %InVec, <i64 1, i64 2, i64 4, i64 8>
/external/llvm-project/llvm/test/Transforms/InstCombine/X86/
Dx86-pshufb.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
10 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
14 define <32 x i8> @identity_test_avx2(<32 x i8> %InVec) {
18 …%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 …
22 define <64 x i8> @identity_test_avx512(<64 x i8> %InVec) {
26 …%1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 1, i8 …
32 define <16 x i8> @fold_to_zero_vector(<16 x i8> %InVec) {
36 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
40 define <32 x i8> @fold_to_zero_vector_avx2(<32 x i8> %InVec) {
44 …%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 -128, i8 …
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InterleavedAccess.cpp527 static void concatSubVector(Value **Vec, ArrayRef<Instruction *> InVec, in concatSubVector() argument
531 Vec[i] = InVec[i]; in concatSubVector()
538 InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32)); in concatSubVector()
548 ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix, in deinterleave8bitStride3() argument
574 concatSubVector(Vec, InVec, VecElems, Builder); in deinterleave8bitStride3()
634 ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix, in interleave8bitStride3() argument
664 InVec[0], UndefValue::get(InVec[0]->getType()), VPAlign2); in interleave8bitStride3()
666 InVec[1], UndefValue::get(InVec[1]->getType()), VPAlign3); in interleave8bitStride3()
667 Vec[2] = InVec[2]; in interleave8bitStride3()
DX86ISelLowering.cpp19549 SDValue InVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecInVT, Src); in LowerI64IntToFP_AVX512DQ() local
19552 {Op.getOperand(0), InVec}); in LowerI64IntToFP_AVX512DQ()
19559 SDValue CvtVec = DAG.getNode(Op.getOpcode(), dl, VecVT, InVec); in LowerI64IntToFP_AVX512DQ()
49162 SDValue InVec = N->getOperand(0); in combineExtractSubvector() local
49164 SDValue InVecBC = peekThroughBitcasts(InVec); in combineExtractSubvector()
49165 EVT InVecVT = InVec.getValueType(); in combineExtractSubvector()
49195 if (ISD::isBuildVectorAllZeros(InVec.getNode())) in combineExtractSubvector()
49198 if (ISD::isBuildVectorAllOnes(InVec.getNode())) { in combineExtractSubvector()
49204 if (InVec.getOpcode() == ISD::BUILD_VECTOR) in combineExtractSubvector()
49207 InVec.getNode()->ops().slice(IdxVal, VT.getVectorNumElements())); in combineExtractSubvector()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InterleavedAccess.cpp521 static void concatSubVector(Value **Vec, ArrayRef<Instruction *> InVec, in concatSubVector() argument
525 Vec[i] = InVec[i]; in concatSubVector()
532 InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32)); in concatSubVector()
542 ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix, in deinterleave8bitStride3() argument
568 concatSubVector(Vec, InVec, VecElems, Builder); in deinterleave8bitStride3()
628 ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix, in interleave8bitStride3() argument
658 InVec[0], UndefValue::get(InVec[0]->getType()), VPAlign2); in interleave8bitStride3()
660 InVec[1], UndefValue::get(InVec[1]->getType()), VPAlign3); in interleave8bitStride3()
661 Vec[2] = InVec[2]; in interleave8bitStride3()
DX86ISelLowering.cpp7342 SDValue InVec = N.getOperand(0); in getFauxShuffleMask() local
7352 Ops.push_back(InVec); in getFauxShuffleMask()
7372 Ops.push_back(InVec); in getFauxShuffleMask()
18605 SDValue InVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecInVT, Src); in LowerI64IntToFP_AVX512DQ() local
18608 {Op.getOperand(0), InVec}); in LowerI64IntToFP_AVX512DQ()
18615 SDValue CvtVec = DAG.getNode(Op.getOpcode(), dl, VecVT, InVec); in LowerI64IntToFP_AVX512DQ()
45675 SDValue InVec = N->getOperand(0); in combineExtractSubvector() local
45676 SDValue InVecBC = peekThroughBitcasts(InVec); in combineExtractSubvector()
45677 EVT InVecVT = InVec.getValueType(); in combineExtractSubvector()
45707 if (ISD::isBuildVectorAllZeros(InVec.getNode())) in combineExtractSubvector()
[all …]
/external/llvm-project/llvm/unittests/CodeGen/
DAArch64SelectionDAGTest.cpp95 auto InVec = DAG->getConstant(0, Loc, InVecVT); in TEST_F() local
96 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
110 auto InVec = DAG->getConstant(0, Loc, InVecVT); in TEST_F() local
111 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
144 auto InVec = DAG->getConstant(1, Loc, InVecVT); in TEST_F() local
145 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
158 auto InVec = DAG->getConstant(1, Loc, InVecVT); in TEST_F() local
159 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp12182 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
12189 return InVec; in visitINSERT_VECTOR_ELT()
12191 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
12209 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
12210 && isa<ConstantSDNode>(InVec.getOperand(2))) { in visitINSERT_VECTOR_ELT()
12212 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue(); in visitINSERT_VECTOR_ELT()
12216 InVec.getOperand(0), InVal, EltNo); in visitINSERT_VECTOR_ELT()
12218 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
12219 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2)); in visitINSERT_VECTOR_ELT()
12229 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
[all …]
DLegalizeVectorTypes.cpp1944 SDValue InVec = N->getOperand(0); in SplitVecOp_TruncateHelper() local
1945 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper()
1966 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL); in SplitVecOp_TruncateHelper()
2382 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops); in WidenVecRes_Convert() local
2384 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
2385 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags); in WidenVecRes_Convert()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1888 SDValue InVec = N->getOperand(0); in PerformDAGCombine() local
1894 return InVec; in PerformDAGCombine()
1896 EVT VT = InVec.getValueType(); in PerformDAGCombine()
1911 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1912 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1913 InVec.getNode()->op_end()); in PerformDAGCombine()
1914 } else if (InVec.isUndef()) { in PerformDAGCombine()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1894 SDValue InVec = N->getOperand(0); in PerformDAGCombine() local
1900 return InVec; in PerformDAGCombine()
1902 EVT VT = InVec.getValueType(); in PerformDAGCombine()
1917 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1918 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1919 InVec.getNode()->op_end()); in PerformDAGCombine()
1920 } else if (InVec.isUndef()) { in PerformDAGCombine()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1997 SDValue InVec = N->getOperand(0); in PerformDAGCombine() local
2004 return InVec; in PerformDAGCombine()
2006 EVT VT = InVec.getValueType(); in PerformDAGCombine()
2021 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2022 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
2023 InVec.getNode()->op_end()); in PerformDAGCombine()
2024 } else if (InVec.isUndef()) { in PerformDAGCombine()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp3246 SDValue InVec = Op.getOperand(0); in computeKnownBits() local
3248 EVT VecVT = InVec.getValueType(); in computeKnownBits()
3260 Known = computeKnownBits(InVec, DemandedElt, Depth + 1); in computeKnownBits()
3263 Known = computeKnownBits(InVec, Depth + 1); in computeKnownBits()
3270 SDValue InVec = Op.getOperand(0); in computeKnownBits() local
3292 Known2 = computeKnownBits(InVec, VectorElts, Depth + 1); in computeKnownBits()
3298 Known = computeKnownBits(InVec, Depth + 1); in computeKnownBits()
3859 SDValue InVec = Op.getOperand(0); in ComputeNumSignBits() local
3883 Tmp2 = ComputeNumSignBits(InVec, VectorElts, Depth + 1); in ComputeNumSignBits()
3888 Tmp = ComputeNumSignBits(InVec, Depth + 1); in ComputeNumSignBits()
[all …]
DDAGCombiner.cpp16850 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
16855 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
16866 InVec == InVal.getOperand(0) && EltNo == InVal.getOperand(1)) in visitINSERT_VECTOR_ELT()
16867 return InVec; in visitINSERT_VECTOR_ELT()
16873 if (InVec.isUndef() && TLI.shouldSplatInsEltVarIndex(VT)) { in visitINSERT_VECTOR_ELT()
16892 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
16893 && isa<ConstantSDNode>(InVec.getOperand(2))) { in visitINSERT_VECTOR_ELT()
16894 unsigned OtherElt = InVec.getConstantOperandVal(2); in visitINSERT_VECTOR_ELT()
16898 InVec.getOperand(0), InVal, EltNo); in visitINSERT_VECTOR_ELT()
16900 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
[all …]
DLegalizeVectorTypes.cpp2518 SDValue InVec = N->getOperand(OpNo); in SplitVecOp_TruncateHelper() local
2519 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper()
2554 GetSplitVector(InVec, InLoVec, InHiVec); in SplitVecOp_TruncateHelper()
3270 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops); in WidenVecRes_Convert() local
3272 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
3273 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags); in WidenVecRes_Convert()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp2671 SDValue InVec = N->getOperand(OpNo); in SplitVecOp_TruncateHelper() local
2672 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper()
2703 GetSplitVector(InVec, InLoVec, InHiVec); in SplitVecOp_TruncateHelper()
3437 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops); in WidenVecRes_Convert() local
3439 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
3440 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags); in WidenVecRes_Convert()
DSelectionDAG.cpp3252 SDValue InVec = Op.getOperand(0); in computeKnownBits() local
3254 EVT VecVT = InVec.getValueType(); in computeKnownBits()
3274 Known = computeKnownBits(InVec, DemandedSrcElts, Depth + 1); in computeKnownBits()
3283 SDValue InVec = Op.getOperand(0); in computeKnownBits() local
3301 Known2 = computeKnownBits(InVec, DemandedVecElts, Depth + 1); in computeKnownBits()
3841 SDValue InVec = Op.getOperand(0); in ComputeNumSignBits() local
3861 Tmp2 = ComputeNumSignBits(InVec, DemandedVecElts, Depth + 1); in ComputeNumSignBits()
3868 SDValue InVec = Op.getOperand(0); in ComputeNumSignBits() local
3870 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits()
3889 return ComputeNumSignBits(InVec, DemandedSrcElts, Depth + 1); in ComputeNumSignBits()
DDAGCombiner.cpp17964 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
17969 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
17980 InVec == InVal.getOperand(0) && EltNo == InVal.getOperand(1)) in visitINSERT_VECTOR_ELT()
17981 return InVec; in visitINSERT_VECTOR_ELT()
17986 if (InVec.isUndef() && TLI.shouldSplatInsEltVarIndex(VT)) { in visitINSERT_VECTOR_ELT()
18014 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
18015 && isa<ConstantSDNode>(InVec.getOperand(2))) { in visitINSERT_VECTOR_ELT()
18016 unsigned OtherElt = InVec.getConstantOperandVal(2); in visitINSERT_VECTOR_ELT()
18020 InVec.getOperand(0), InVal, EltNo); in visitINSERT_VECTOR_ELT()
18022 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
[all …]

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