| /external/llvm-project/llvm/lib/CodeGen/ |
| D | UnreachableBlockElim.cpp | 176 Register InputReg = Input.getReg(); in runOnMachineFunction() local
181 if (InputReg != OutputReg) { in runOnMachineFunction()
185 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
187 MRI.replaceRegWith(OutputReg, InputReg); in runOnMachineFunction()
196 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
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| D | TargetInstrInfo.cpp | 1315 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregInputs()
1320 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1332 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1333 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1334 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | UnreachableBlockElim.cpp | 178 Register InputReg = Input.getReg(); in runOnMachineFunction() local
183 if (InputReg != OutputReg) { in runOnMachineFunction()
187 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
189 MRI.replaceRegWith(OutputReg, InputReg); in runOnMachineFunction()
198 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
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| D | TargetInstrInfo.cpp | 1242 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregInputs()
1247 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1259 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1260 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1261 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 1001 Register InputReg = MRI.createGenericVirtualRegister(ArgTy); in passSpecialInputs() local
1004 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
1007 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder); in passSpecialInputs()
1011 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
1051 Register InputReg; in passSpecialInputs() local
1053 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
1054 LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX, in passSpecialInputs()
1064 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y; in passSpecialInputs()
1073 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z; in passSpecialInputs()
1076 if (!InputReg) { in passSpecialInputs()
[all …]
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| D | SIFixSGPRCopies.cpp | 857 Register InputReg = MI.getOperand(i).getReg(); in processPHINode() local
858 MachineInstr *Def = MRI->getVRegDef(InputReg); in processPHINode()
859 if (TRI->isVectorRegister(*MRI, InputReg)) { in processPHINode()
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| D | SIISelLowering.cpp | 2711 SDValue InputReg; in passSpecialInputs() local
2714 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
2719 InputReg = getImplicitArgPtr(DAG, DL); in passSpecialInputs()
2723 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
2729 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg, in passSpecialInputs()
2759 SDValue InputReg; in passSpecialInputs() local
2764 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
2770 InputReg = InputReg.getNode() ? in passSpecialInputs()
2771 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y; in passSpecialInputs()
2778 InputReg = InputReg.getNode() ? in passSpecialInputs()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2363 unsigned InputReg = getRegForValue(I->getOperand(0)); in X86SelectTrunc() local
2364 if (!InputReg) in X86SelectTrunc()
2370 updateValueMap(I, InputReg); in X86SelectTrunc()
2382 TII.get(TargetOpcode::COPY), CopyReg).addReg(InputReg); in X86SelectTrunc()
2383 InputReg = CopyReg; in X86SelectTrunc()
2389 InputReg, KillInputReg, in X86SelectTrunc()
2447 unsigned InputReg = getRegForValue(Op); in fastLowerIntrinsicCall() local
2448 if (InputReg == 0) in fastLowerIntrinsicCall()
2471 InputReg = fastEmitInst_ri(X86::VCVTPS2PHrr, RC, InputReg, false, 4); in fastLowerIntrinsicCall()
2477 .addReg(InputReg, RegState::Kill); in fastLowerIntrinsicCall()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 1150 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregInputs()
1155 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1165 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1166 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1167 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2556 Register InputReg = getRegForValue(I->getOperand(0)); in X86SelectTrunc() local
2557 if (!InputReg) in X86SelectTrunc()
2563 updateValueMap(I, InputReg); in X86SelectTrunc()
2569 InputReg, false, in X86SelectTrunc()
2627 Register InputReg = getRegForValue(Op); in fastLowerIntrinsicCall() local
2628 if (InputReg == 0) in fastLowerIntrinsicCall()
2653 InputReg = fastEmitInst_ri(Opc, RC, InputReg, false, 4); in fastLowerIntrinsicCall()
2660 .addReg(InputReg, RegState::Kill); in fastLowerIntrinsicCall()
2668 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg, in fastLowerIntrinsicCall()
2672 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2540 unsigned InputReg = getRegForValue(I->getOperand(0)); in X86SelectTrunc() local
2541 if (!InputReg) in X86SelectTrunc()
2547 updateValueMap(I, InputReg); in X86SelectTrunc()
2553 InputReg, false, in X86SelectTrunc()
2611 unsigned InputReg = getRegForValue(Op); in fastLowerIntrinsicCall() local
2612 if (InputReg == 0) in fastLowerIntrinsicCall()
2635 InputReg = fastEmitInst_ri(X86::VCVTPS2PHrr, RC, InputReg, false, 4); in fastLowerIntrinsicCall()
2641 .addReg(InputReg, RegState::Kill); in fastLowerIntrinsicCall()
2649 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::SIGN_EXTEND, InputReg, in fastLowerIntrinsicCall()
2653 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 812 unsigned InputReg = MI.getOperand(i).getReg(); in processPHINode() local
813 MachineInstr *Def = MRI->getVRegDef(InputReg); in processPHINode()
814 if (TRI->isVectorRegister(*MRI, InputReg)) { in processPHINode()
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| D | SIISelLowering.cpp | 2493 SDValue InputReg; in passSpecialInputs() local
2496 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
2501 InputReg = getImplicitArgPtr(DAG, DL); in passSpecialInputs()
2505 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
2508 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg, in passSpecialInputs()
2537 SDValue InputReg; in passSpecialInputs() local
2542 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
2548 InputReg = InputReg.getNode() ? in passSpecialInputs()
2549 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y; in passSpecialInputs()
2556 InputReg = InputReg.getNode() ? in passSpecialInputs()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 410 RegSubRegPairAndIdx &InputReg) const;
949 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs() argument
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 514 RegSubRegPairAndIdx &InputReg) const;
1160 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs() argument
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 521 RegSubRegPairAndIdx &InputReg) const;
1183 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs() argument
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 69 RegSubRegPairAndIdx &InputReg) const override;
|
| D | ARMBaseInstrInfo.cpp | 4622 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs()
4633 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
4634 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
4635 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 73 RegSubRegPairAndIdx &InputReg) const override;
|
| D | ARMBaseInstrInfo.cpp | 5273 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs()
5286 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
5287 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
5288 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1262 unsigned InputReg = getRegForValue(I->getOperand(0)); in selectCast() local
1263 if (!InputReg) in selectCast()
1270 Opcode, InputReg, InputRegIsKill); in selectCast()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 75 RegSubRegPairAndIdx &InputReg) const override;
|
| D | ARMBaseInstrInfo.cpp | 5309 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs()
5322 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
5323 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
5324 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1554 Register InputReg = getRegForValue(I->getOperand(0)); in selectCast() local
1555 if (!InputReg) in selectCast()
1562 Opcode, InputReg, InputRegIsKill); in selectCast()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1508 unsigned InputReg = getRegForValue(I->getOperand(0)); in selectCast() local
1509 if (!InputReg) in selectCast()
1516 Opcode, InputReg, InputRegIsKill); in selectCast()
|