Home
last modified time | relevance | path

Searched refs:MRM4r (Results 1 – 25 of 45) sorted by relevance

12

/external/llvm/lib/Target/X86/
DX86InstrControl.td135 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
142 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
149 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
260 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
310 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
322 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
DX86InstrShiftRotate.td20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
57 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
59 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td378 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
448 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
450 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
453 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
DX86InstrFPStack.td274 def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;
275 def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
276 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;
589 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
DX86InstrMMX.td505 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
508 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrControl.td127 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
134 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
141 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
151 def JMP64r_REX : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
161 def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst",
170 def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst",
178 def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst",
DX86InstrShiftRotate.td19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td358 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
425 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
427 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
430 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
719 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
722 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
DX86InstrFPStack.td323 def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;
324 def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;
325 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;
675 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrControl.td127 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
134 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
141 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
151 def JMP64r_REX : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
161 def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst",
170 def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst",
178 def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst",
DX86InstrShiftRotate.td19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td348 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
415 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
417 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
420 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
709 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
712 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
DX86InstrFPStack.td329 def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;
330 def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;
331 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;
678 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
/external/llvm-project/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
109 "shl $dst, CL", 0xD2, MRM4r,
/external/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
109 "shl $dst, CL", 0xD2, MRM4r,
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
687 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp871 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1022 case X86II::MRM4r: case X86II::MRM5r: in DetermineREXPrefix()
1357 case X86II::MRM4r: case X86II::MRM5r: in encodeInstruction()
/external/llvm-project/llvm/utils/TableGen/
DX86RecognizableInstr.h124 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, enumerator
DX86RecognizableInstr.cpp658 case X86Local::MRM4r: in emitInstructionSpecifier()
796 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
DX86FoldTablesEmitter.cpp433 (MemFormNum == X86Local::MRM4m && RegFormNum == X86Local::MRM4r) || in areOppositeForms()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h667 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 enumerator
1057 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1088 case X86II::MRM4r: in emitVEXOpcodePrefix()
1243 case X86II::MRM4r: in determineREXPrefix()
1632 case X86II::MRM4r: in encodeInstruction()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h718 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7 enumerator
1130 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1120 case X86II::MRM4r: in emitVEXOpcodePrefix()
1280 case X86II::MRM4r: in emitREXPrefix()
1653 case X86II::MRM4r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
719 case X86Local::MRM4r: in emitInstructionSpecifier()
854 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()

12