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Searched refs:RegList (Results 1 – 25 of 71) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
42 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
199 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
202 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
203 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
208 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
209 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
215 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
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DThumb2ITBlockPass.cpp83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
84 RegList LocalDefs; in INITIALIZE_PASS()
85 RegList LocalUses; in INITIALIZE_PASS()
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
/external/llvm/lib/Target/ARM/
DARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
206 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
209 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
210 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
221 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
224 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
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/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
197 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
200 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
214 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
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DThumb2ITBlockPass.cpp83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
84 RegList LocalDefs; in INITIALIZE_PASS()
85 RegList LocalUses; in INITIALIZE_PASS()
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
/external/llvm/lib/Target/X86/
DX86CallingConv.h53 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
54 static const unsigned NumRegs = sizeof(RegList)/sizeof(RegList[0]); in CC_X86_32_MCUInReg()
72 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
88 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
93 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.h89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
91 RegList = XRegList; in CC_AArch64_Custom_Block()
93 RegList = HRegList; in CC_AArch64_Custom_Block()
95 RegList = SRegList; in CC_AArch64_Custom_Block()
97 RegList = DRegList; in CC_AArch64_Custom_Block()
99 RegList = QRegList; in CC_AArch64_Custom_Block()
115 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); in CC_AArch64_Custom_Block()
127 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
/external/llvm-project/llvm/utils/TableGen/
DCallingConvEmitter.cpp126 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
127 if (RegList->size() == 1) { in EmitAction()
129 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; in EmitAction()
134 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
136 O << getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
147 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
149 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in EmitAction()
153 if (RegList->size() == 1) { in EmitAction()
155 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
165 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
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/external/llvm/utils/TableGen/
DCallingConvEmitter.cpp113 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
114 if (RegList->size() == 1) { in EmitAction()
116 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; in EmitAction()
121 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
123 O << getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
134 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
136 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in EmitAction()
139 if (RegList->size() == 1) { in EmitAction()
141 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
151 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.cpp90 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
92 RegList = XRegList; in CC_AArch64_Custom_Block()
94 RegList = HRegList; in CC_AArch64_Custom_Block()
96 RegList = SRegList; in CC_AArch64_Custom_Block()
98 RegList = DRegList; in CC_AArch64_Custom_Block()
100 RegList = QRegList; in CC_AArch64_Custom_Block()
120 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg); in CC_AArch64_Custom_Block()
146 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64CallingConvention.cpp137 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
139 RegList = XRegList; in CC_AArch64_Custom_Block()
141 RegList = HRegList; in CC_AArch64_Custom_Block()
143 RegList = SRegList; in CC_AArch64_Custom_Block()
145 RegList = DRegList; in CC_AArch64_Custom_Block()
147 RegList = QRegList; in CC_AArch64_Custom_Block()
149 RegList = ZRegList; in CC_AArch64_Custom_Block()
169 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg); in CC_AArch64_Custom_Block()
196 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
40 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
101 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); in CC_X86_32_MCUInReg()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/external/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
40 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
101 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); in CC_X86_32_MCUInReg()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/external/vixl/src/aarch64/
Doperands-aarch64.h53 CPURegList(CPURegister::RegisterType type, unsigned size, RegList list) in CPURegList()
87 RegList list = (static_cast<RegList>(1) << number_of_registers) - 1;
90 list |= (static_cast<RegList>(1) << kSPRegInternalCode);
185 RegList GetList() const { in GetList()
189 VIXL_DEPRECATED("GetList", RegList list() const) { return GetList(); }
191 void SetList(RegList new_list) { in SetList()
195 VIXL_DEPRECATED("SetList", void set_list(RegList new_list)) { in set_list()
206 CPURegister PopLowestIndex(RegList mask = ~static_cast<RegList>(0));
207 CPURegister PopHighestIndex(RegList mask = ~static_cast<RegList>(0));
231 return (((static_cast<RegList>(1) << code) & list_) != 0); in IncludesAliasOf()
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Doperands-aarch64.cc33 CPURegister CPURegList::PopLowestIndex(RegList mask) { in PopLowestIndex()
34 RegList list = list_ & mask; in PopLowestIndex()
43 CPURegister CPURegList::PopHighestIndex(RegList mask) { in PopHighestIndex()
44 RegList list = list_ & mask; in PopHighestIndex()
Dregisters-aarch64.cc185 RegList unique_regs = 0; in AreAliased()
186 RegList unique_vregs = 0; in AreAliased()
187 RegList unique_pregs = 0; in AreAliased()
Dmacro-assembler-aarch64.cc2939 RegList reg_list = list.GetList(); in Include()
2954 RegList include = in Include()
2967 RegList include = in Include()
2977 RegList include = 0; in Include()
2978 RegList include_v = 0; in Include()
2979 RegList include_p = 0; in Include()
2984 RegList bit = regs[i].GetBit(); in Include()
3017 RegList exclude = in Exclude()
3027 RegList exclude_v = in Exclude()
3037 RegList exclude = 0; in Exclude()
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Dregisters-aarch64.h39 typedef uint64_t RegList; typedef
40 static const int kRegListSizeInBits = sizeof(RegList) * 8;
119 RegList GetBit() const { in GetBit()
122 return static_cast<RegList>(1) << code_; in GetBit()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMELFStreamer.cpp73 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
137 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
139 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
145 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
147 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
149 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
369 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
438 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
649 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
651 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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DARMTargetStreamer.cpp56 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h489 RegList PopulateRegisterArray(Register* w,
494 RegList allowed);
497 RegList PopulateVRegisterArray(VRegister* s,
502 RegList allowed);
513 RegList reg_list,
518 RegList reg_list,
Dtest-utils-aarch64.cc487 RegList PopulateRegisterArray(Register* w, in PopulateRegisterArray()
492 RegList allowed) { in PopulateRegisterArray()
493 RegList list = 0; in PopulateRegisterArray()
518 RegList PopulateVRegisterArray(VRegister* s, in PopulateVRegisterArray()
523 RegList allowed) { in PopulateVRegisterArray()
524 RegList list = 0; in PopulateVRegisterArray()
549 void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) { in Clobber()
572 void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) { in ClobberFP()
/external/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp35 typedef SmallVector<unsigned, 4> RegList; typedef
36 typedef DenseMap<unsigned, RegList> SourceMap;
86 static void removeRegsFromMap(Reg2MIMap &Map, const RegList &Regs, in removeRegsFromMap()
247 RegList &DestList = SrcMap[Src]; in CopyPropagateBlock()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMELFStreamer.cpp85 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
159 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
165 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
167 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
169 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
397 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
467 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
749 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
751 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMELFStreamer.cpp85 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
159 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
165 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
167 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
169 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
389 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
459 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
741 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
743 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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