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Searched refs:SHUF (Results 1 – 25 of 28) sorted by relevance

/external/llvm-project/llvm/test/Transforms/InstCombine/
D	insert-const-shuf.ll	31 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> %base, <4 x i32> <i32 undef, i32 undef, i32 u… 32 ; CHECK-NEXT: ret <4 x i32> [[SHUF]] 42 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x float> %x, <4 x float> <float undef, float 1.000… 43 ; CHECK-NEXT: [[INS:%.]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 0 55 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x float> %x, <4 x float> <float undef, float 1.000… 56 ; CHECK-NEXT: [[INS:%.]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 3 68 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x float> %x, <4 x float> <float 1.000000e+00, floa… 69 ; CHECK-NEXT: [[INS:%.]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 3 82 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <3 x float> %x, <3 x float> <float undef, float 1.000… 83 ; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x float> [[SHUF]], float 4.200000e+01, i2 1 [all …]
D	nsw.ll	`105 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <3 x i32> <i32 1, … 106 ; CHECK-NEXT: [[T3:%.]] = shl nuw nsw <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17> 121 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <3 x i32> <i32 1, … 122 ; CHECK-NEXT: [[T3:%.]] = shl <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17>`
D	trunc.ll	911 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[X:%.]], <4 x i32> <i32 undef, i32 3634, … 912 ; CHECK-NEXT: [[TRUNC:%.]] = trunc <4 x i32> [[SHUF]] to <4 x i8> 953 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <3 x i33> [[X:%.]], <3 x i33> undef, <3 x i32> <i32 … 954 ; CHECK-NEXT: [[TRUNC:%.]] = trunc <3 x i33> [[SHUF]] to <3 x i31> 966 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i16> [[V:%.]], <4 x i16> undef, <8 x i32> zeroi… 967 ; CHECK-NEXT: [[TR:%.*]] = trunc <8 x i16> [[SHUF]] to <8 x i8>
D	assume.ll	`374 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i8> [[X:%.]], <4 x i8> undef, <4 x i32> <i32 1,… 375 ; CHECK-NEXT: [[T2:%.*]] = bitcast <4 x i8> [[SHUF]] to i32`
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
D	legalize-shuffle-vector.mir	15 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflem… 16 ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>) 37 …; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], shufflem… 38 ; CHECK: $q0 = COPY [[SHUF]](<2 x s64>) 59 …; CHECK: [[SHUF:%[0-9]+]]:_(<2 x p0>) = G_SHUFFLE_VECTOR [[COPY]](<2 x p0>), [[COPY1]], shufflemas… 60 ; CHECK: $q0 = COPY [[SHUF]](<2 x p0>) 81 …; CHECK: [[SHUF:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<16 x s8>), [[COPY1]], shufflem… 82 ; CHECK: $q0 = COPY [[SHUF]](<16 x s8>) 103 …; CHECK: [[SHUF:%[0-9]+]]:_(<8 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<8 x s16>), [[COPY1]], shufflem… 104 ; CHECK: $q0 = COPY [[SHUF]](<8 x s16>)
D	prelegalizercombiner-shuffle-vector.mir	77 …; CHECK: [[SHUF:%[0-9]+]]:_(<6 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflem… 78 ; CHECK: RET_ReallyLR implicit [[SHUF]](<6 x s32>) 118 …; CHECK: [[SHUF:%[0-9]+]]:_(<6 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflem… 119 ; CHECK: RET_ReallyLR implicit [[SHUF]](<6 x s32>) 138 …; CHECK: [[SHUF:%[0-9]+]]:_(<6 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflem… 139 ; CHECK: RET_ReallyLR implicit [[SHUF]](<6 x s32>) 219 …; CHECK: [[SHUF:%[0-9]+]]:_(<8 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflem… 220 ; CHECK: RET_ReallyLR implicit [[SHUF]](<8 x s32>) 260 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflem… 261 ; CHECK: RET_ReallyLR implicit [[SHUF]](<4 x s32>) [all …]
D	postlegalizer-lowering-uzp.mir	`67 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflem… 68 ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>) 91 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflem… 92 ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>)`
D	postlegalizercombiner-extractvec-faddp.mir	`143 …; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[DEF]], shufflemas… 144 ; CHECK: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[SHUF]], [[COPY]] 174 …; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[DEF]], shufflemas… 175 ; CHECK: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[SHUF]], [[COPY]]`
D	legalize-select.mir	`141 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemas… 144 ; CHECK: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]] 145 ; CHECK: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]`
D	prelegalizercombiner-undef.mir	`219 …; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<2 x s32>), [[COPY]], shufflemas… 220 ; CHECK: $d0 = COPY [[SHUF]](<2 x s32>)`
D	postlegalizer-lowering-zip.mir	`216 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflem… 217 ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>)`
D	postlegalizer-lowering-shuffle-splat.mir	`275 …; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemas… 276 ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>)`
/external/llvm-project/llvm/test/CodeGen/X86/
D	phaddsub.ll	`8 …ple=x86_64-unknown -mattr=+avx2,fast-variable-shuffle \| FileCheck %s --check-prefixes=AVX,AVX2-SHUF 145 ; AVX2-SHUF-LABEL: phaddd6: 146 ; AVX2-SHUF: # %bb.0: 147 ; AVX2-SHUF-NEXT: vpshufd {{.#+}} xmm1 = xmm0[1,1,1,1] 148 ; AVX2-SHUF-NEXT: vpaddd %xmm1, %xmm0, %xmm0 149 ; AVX2-SHUF-NEXT: retq 259 ; AVX2-SHUF-LABEL: phsubd4: 260 ; AVX2-SHUF: # %bb.0: 261 ; AVX2-SHUF-NEXT: vpshufd {{.#+}} xmm1 = xmm0[1,1,1,1] 262 ; AVX2-SHUF-NEXT: vpsubd %xmm1, %xmm0, %xmm0 [all …]`
/external/mesa3d/src/mesa/tnl/
D	t_vertex_sse.c	92 sse_shufps(&p->func, dest, get_identity(p), SHUF(X,Y,Z,W) ); in emit_load4f_3() 93 sse_shufps(&p->func, dest, dest, SHUF(Y,Z,X,W) ); in emit_load4f_3() 113 sse_shufps(&p->func, dest, get_identity(p), SHUF(X,Y,Z,W) ); in emit_load4f_1() 134 sse_shufps(&p->func, dest, dest, SHUF(X,X,X,X)); in emit_load3f_3() 230 sse_shufps(&p->func, arg0, arg0, SHUF(Z,Z,Z,Z) ); /* NOTE! destructive */ in emit_store3f() 482 sse_shufps(&p->func, temp, temp, SHUF(X,Y,W,Z)); in build_vertex_emit() 495 sse_shufps(&p->func, temp, temp, SHUF(X,X,X,X)); in build_vertex_emit() 513 sse_shufps(&p->func, temp, temp, SHUF(Z,Y,X,W)); in build_vertex_emit() 528 sse_shufps(&p->func, temp, temp, SHUF(W,X,Y,Z)); in build_vertex_emit() 538 sse_shufps(&p->func, temp, temp, SHUF(W,Z,Y,X)); in build_vertex_emit() [all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	regbankselect-shuffle-vector.mir	`15 …; CHECK: [[SHUF:%[0-9]+]]:sgpr(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shuff… 32 …; CHECK: [[SHUF:%[0-9]+]]:vgpr(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY2]](<2 x s16>), [[COPY1]], shuf… 49 …; CHECK: [[SHUF:%[0-9]+]]:vgpr(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY2]], shuff… 65 …; CHECK: [[SHUF:%[0-9]+]]:vgpr(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shuff…`
D	legalize-shuffle-vector.s16.mir	27 …; GFX9: [[SHUF:%[0-9]+]]:_(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shufflema… 28 ; GFX9: $vgpr0 = COPY [[SHUF]](<2 x s16>) 64 …; GFX9: [[SHUF:%[0-9]+]]:_(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shufflema… 65 ; GFX9: $vgpr0 = COPY [[SHUF]](<2 x s16>) 101 …; GFX9: [[SHUF:%[0-9]+]]:_(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shufflema… 102 ; GFX9: $vgpr0 = COPY [[SHUF]](<2 x s16>) 141 …; GFX9: [[SHUF:%[0-9]+]]:_(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shufflema… 142 ; GFX9: $vgpr0 = COPY [[SHUF]](<2 x s16>) 181 …; GFX9: [[SHUF:%[0-9]+]]:_(<2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s16>), [[COPY1]], shufflema… 182 ; GFX9: $vgpr0 = COPY [[SHUF]](<2 x s16>) [all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/
D	shufflevector.ll	22 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <3 x i32> [[X:%.]], <3 x i32> zeroinitializer, <4 x … 23 ; CHECK-NEXT: ret <4 x i32> [[SHUF]] 82 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[SPLAT]], <4 x i32> undef, <8 x i32> <i32 … 83 ; CHECK-NEXT: ret <8 x i32> [[SHUF]] 93 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[SPLAT]], <4 x i32> [[Y:%.]], <4 x i32> <… 94 ; CHECK-NEXT: ret <4 x i32> [[SHUF]] 104 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[Y:%.]], <4 x i32> [[SPLAT]], <4 x i32> <… 105 ; CHECK-NEXT: ret <4 x i32> [[SHUF]] 115 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[SPLAT]], <4 x i32> undef, <4 x i32> <i32 … 116 ; CHECK-NEXT: ret <4 x i32> [[SHUF]] [all …]
/external/llvm-project/llvm/test/Transforms/VectorCombine/X86/
D	shuffle.ll	9 ; SSE-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[V:%.]], <4 x i32> undef, <4 x i32> <i32 3,… 10 ; SSE-NEXT: [[R:%.]] = bitcast <4 x i32> [[SHUF]] to <16 x i8> 40 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <2 x i32> [[V:%.]], <2 x i32> undef, <4 x i32> <i32 … 41 ; CHECK-NEXT: [[R:%.]] = bitcast <4 x i32> [[SHUF]] to <16 x i8> 53 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[V:%.]], <4 x i32> undef, <4 x i32> <i32 … 54 ; CHECK-NEXT: [[R:%.]] = bitcast <4 x i32> [[SHUF]] to i128 81 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[V:%.]], <4 x i32> undef, <4 x i32> <i32 … 82 ; CHECK-NEXT: call void @use(<4 x i32> [[SHUF]]) 83 ; CHECK-NEXT: [[R:%.]] = bitcast <4 x i32> [[SHUF]] to <16 x i8>
D	no-sse.ll	`8 ; CHECK-NEXT: [[SHUF:%.]] = shufflevector <4 x i32> [[V:%.]], <4 x i32> undef, <4 x i32> <i32 … 9 ; CHECK-NEXT: [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <4 x float>`
/external/mesa3d/src/gallium/auxiliary/translate/
D	translate_sse.c	255 SHUF(X, Y, Z, W)); in emit_load_float32() 271 SHUF(X, Y, Z, W)); in emit_load_float32() 272 sse_shufps(p->func, data, data, SHUF(Y, Z, X, W)); in emit_load_float32() 298 SHUF(X, Y, Z, W)); in emit_load_float64to32() 305 SHUF(X, Y, Z, W)); in emit_load_float64to32() 659 SHUF(swizzle[0], swizzle[1], swizzle[2], swizzle[3])); in translate_attr_convert() 687 sse_shufps(p->func, dataXMM, dataXMM, SHUF(1, 1, 2, 3)); in translate_attr_convert() 705 sse_shufps(p->func, dataXMM, dataXMM, SHUF(2, 2, 2, 3)); in translate_attr_convert() 715 sse_shufps(p->func, dataXMM, dataXMM, SHUF(3, 3, 3, 3)); in translate_attr_convert() 1039 sse_shufps(p->func, dataXMM, dataXMM, SHUF(2, 1, 0, 3)); in translate_attr_convert()
/external/compiler-rt/lib/tsan/rtl/
D	tsan_rtl.cc	673 #define SHUF(v0, v1, i0, i1, i2, i3) _mm_castps_si128(_mm_shuffle_ps( \ macro 686 const m128 addr0 = SHUF(access, access, 1, 1, 1, 1); in ContainsSameAccessFast() 695 m128 addr_vect = SHUF(shadow0, shadow1, 1, 3, 1, 3); in ContainsSameAccessFast() 699 const m128 rw_mask = SHUF(rw_mask1, rw_mask1, 0, 0, 0, 0); in ContainsSameAccessFast() 710 const m128 epoch = SHUF(epoch1, epoch1, 0, 0, 0, 0); in ContainsSameAccessFast() 716 const m128 epoch_vect = SHUF(shadow0, shadow1, 0, 2, 0, 2); in ContainsSameAccessFast()
/external/llvm-project/compiler-rt/lib/tsan/rtl/
D	tsan_rtl.cpp	760 #define SHUF(v0, v1, i0, i1, i2, i3) _mm_castps_si128(_mm_shuffle_ps( \ macro 773 const m128 addr0 = SHUF(access, access, 1, 1, 1, 1); in ContainsSameAccessFast() 782 m128 addr_vect = SHUF(shadow0, shadow1, 1, 3, 1, 3); in ContainsSameAccessFast() 786 const m128 rw_mask = SHUF(rw_mask1, rw_mask1, 0, 0, 0, 0); in ContainsSameAccessFast() 797 const m128 epoch = SHUF(epoch1, epoch1, 0, 0, 0, 0); in ContainsSameAccessFast() 803 const m128 epoch_vect = SHUF(shadow0, shadow1, 0, 2, 0, 2); in ContainsSameAccessFast()
/external/llvm/test/Transforms/InstCombine/
D	type_pun.ll	`42 ; CHECK-NEXT: %[[SHUF:.]] = shufflevector <16 x i8> %in, <16 x i8> undef, <16 x i32> <i32 6, i32 7… 43 ; CHECK-NEXT: %[[BC:.]] = bitcast <16 x i8> %[[SHUF]] to <4 x i32>`
/external/mesa3d/src/mesa/x86/rtasm/
D	x86sse.h	`134 #define SHUF(_x,_y,_z,_w) (((_x)<<0) \| ((_y)<<2) \| ((_z)<<4) \| ((_w)<<6)) macro`
/external/mesa3d/src/gallium/auxiliary/rtasm/
D	rtasm_x86sse.h	`214 #define SHUF(_x,_y,_z,_w) (((_x)<<0) \| ((_y)<<2) \| ((_z)<<4) \| ((_w)<<6)) macro`

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