| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-smin.mir | 15 ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
16 ; SI: $vgpr0 = COPY [[SMIN]](s32)
20 ; VI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
21 ; VI: $vgpr0 = COPY [[SMIN]](s32)
25 ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
26 ; GFX9: $vgpr0 = COPY [[SMIN]](s32)
76 ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
77 ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
84 ; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[TRUNC1]]
85 ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16)
[all …]
|
| D | regbankselect-smin.mir | 37 ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY2]], [[COPY1]]
38 ; CHECK: $vgpr0 = COPY [[SMIN]](s32)
57 ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY2]]
58 ; CHECK: $vgpr0 = COPY [[SMIN]](s32)
76 ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
77 ; CHECK: $vgpr0 = COPY [[SMIN]](s32)
208 ; CHECK: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY2]], [[COPY1]]
209 ; CHECK: $vgpr0 = COPY [[SMIN]](<2 x s16>)
228 ; CHECK: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY]], [[COPY2]]
229 ; CHECK: $vgpr0 = COPY [[SMIN]](<2 x s16>)
[all …]
|
| D | legalize-ssubsat.mir | 25 ; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
26 ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
46 ; GFX8: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
47 ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]]
94 ; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
95 ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
115 ; GFX8: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
116 ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]]
171 ; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C5]]
172 ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C4]]
[all …]
|
| D | legalize-saddsat.mir | 25 ; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
26 ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
46 ; GFX8: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
47 ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]]
94 ; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
95 ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
115 ; GFX8: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
116 ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]]
171 ; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C5]]
172 ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[SMIN]]
[all …]
|
| D | legalize-fptrunc.mir | 121 ; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
125 ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
201 ; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
205 ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
328 ; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
332 ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
408 ; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2767 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
2783 {ISD::SMIN, MVT::v2i64, 6}, in getMinMaxReductionCost()
2785 {ISD::SMIN, MVT::v4i32, 6}, in getMinMaxReductionCost()
2787 {ISD::SMIN, MVT::v8i16, 4}, in getMinMaxReductionCost()
2789 {ISD::SMIN, MVT::v16i8, 8}, in getMinMaxReductionCost()
2795 {ISD::SMIN, MVT::v2i64, 9}, in getMinMaxReductionCost()
2797 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" in getMinMaxReductionCost()
2799 {ISD::SMIN, MVT::v8i16, 2}, in getMinMaxReductionCost()
2801 {ISD::SMIN, MVT::v16i8, 3}, in getMinMaxReductionCost()
2806 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" in getMinMaxReductionCost()
[all …]
|
| /external/llvm-project/llvm/test/Transforms/IRCE/ |
| D | rc-negative-bound.ll | 120 ; CHECK-NEXT: [[SMIN:%.*]] = select i1 [[TMP3]], i32 [[BOUND]], i32 0
121 ; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[SMIN]], -1
122 ; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[TMP4]], i32 [[SMIN]], i32 -1
210 ; CHECK-NEXT: [[SMIN:%.*]] = select i1 [[TMP0]], i32 [[BOUND]], i32 0
211 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[BOUND]], [[SMIN]]
212 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[SMIN]], -1
213 ; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP2]], i32 [[SMIN]], i32 -1
408 ; CHECK-NEXT: [[SMIN:%.*]] = select i1 [[TMP3]], i32 [[BOUND]], i32 0
409 ; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[SMIN]], -1
410 ; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[TMP4]], i32 [[SMIN]], i32 -1
[all …]
|
| D | non-loop-invariant-rhs-instr.ll | 14 ; CHECK-NEXT: [[SMIN:%.*]] = select i1 [[TMP2]], i64 [[LEN]], i64 0
15 ; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[LEN]], [[SMIN]]
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2331 { ISD::SMIN, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2332 { ISD::SMIN, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2373 { ISD::SMIN, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2374 { ISD::SMIN, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2375 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2376 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2377 { ISD::SMIN, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2378 { ISD::SMIN, MVT::v2i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2459 { ISD::SMIN, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2460 { ISD::SMIN, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | vec_minmax_match.ll | 34 ; (X >s Y) ? 0 : Z ==> (Z >s 0) ? 0 : Z ==> SMIN(Z, 0)
49 ; (X <s Y) ? Z : 0 ==> (Z <s 0) ? Z : 0 ==> SMIN(Z, 0)
162 ; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
177 ; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
|
| /external/XNNPACK/src/qs8-gemm/ |
| D | 4x16c4-aarch64-neondot-ld32.S | 233 SMIN v4.16b, v4.16b, v1.16b
234 SMIN v5.16b, v5.16b, v1.16b
235 SMIN v6.16b, v6.16b, v1.16b
236 SMIN v7.16b, v7.16b, v1.16b
|
| D | 4x16c4-aarch64-neondot-ld64.S | 256 SMIN v4.16b, v4.16b, v1.16b
257 SMIN v5.16b, v5.16b, v1.16b
258 SMIN v6.16b, v6.16b, v1.16b
259 SMIN v7.16b, v7.16b, v1.16b
|
| D | 1x16c4-aarch64-neondot-ld32.S | 85 SMIN v4.16b, v4.16b, v1.16b
|
| D | 1x16c4-aarch64-neondot-ld64.S | 103 SMIN v4.16b, v4.16b, v1.16b
|
| D | 4x16c4-aarch64-neondot-cortex-a55.S | 527 SMIN v4.16b, v4.16b, v1.16b
528 SMIN v5.16b, v5.16b, v1.16b
529 SMIN v6.16b, v6.16b, v1.16b
530 SMIN v7.16b, v7.16b, v1.16b
|
| /external/XNNPACK/src/qs8-igemm/ |
| D | 4x16c4-aarch64-neondot-ld64.S | 279 SMIN v4.16b, v4.16b, v1.16b
280 SMIN v5.16b, v5.16b, v1.16b
281 SMIN v6.16b, v6.16b, v1.16b
282 SMIN v7.16b, v7.16b, v1.16b
|
| D | 4x16c4-aarch64-neondot-cortex-a55.S | 552 SMIN v4.16b, v4.16b, v1.16b
553 SMIN v5.16b, v5.16b, v1.16b
554 SMIN v6.16b, v6.16b, v1.16b
555 SMIN v7.16b, v7.16b, v1.16b
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 325 SMIN, SMAX, UMIN, UMAX, enumerator
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 972 X86_INTRINSIC_DATA(avx512_mask_pmins_b_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
973 X86_INTRINSIC_DATA(avx512_mask_pmins_b_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
974 X86_INTRINSIC_DATA(avx512_mask_pmins_b_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
975 X86_INTRINSIC_DATA(avx512_mask_pmins_d_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
976 X86_INTRINSIC_DATA(avx512_mask_pmins_d_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
977 X86_INTRINSIC_DATA(avx512_mask_pmins_d_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
978 X86_INTRINSIC_DATA(avx512_mask_pmins_q_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
979 X86_INTRINSIC_DATA(avx512_mask_pmins_q_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
980 X86_INTRINSIC_DATA(avx512_mask_pmins_q_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
981 X86_INTRINSIC_DATA(avx512_mask_pmins_w_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
[all …]
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | minmax-fold.ll | 225 ; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11)
294 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
366 ; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
383 ; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
400 ; (X >s C1) ? SMIN(X, C2) : C1 ==> SMAX(SMIN(X, C2), C1)
417 ; (X <s C1) ? SMAX(X, C2) : C1 ==> SMIN(SMAX(X, C1), C2)
|
| D | select_meta.ll | 168 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
|
| /external/llvm-project/llvm/test/Transforms/HardwareLoops/ARM/ |
| D | simple-do.ll | 149 ; CHECK: [[SMIN:%[^ ]+]] = select i1 [[CMP]], i32 %n, i32 2
150 ; CHECK: [[SUB:%[^ ]+]] = sub i32 [[ROUND]], [[SMIN]]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 445 SMIN, SMAX, UMIN, UMAX, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 575 SMIN, enumerator
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | select.ll | 608 ; SMIN(SMIN(x, y), x) -> SMIN(x, y)
1273 ; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11)
1321 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
|