| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 954 Register SuperReg = MI->getOperand(0).getReg(); in buildSGPRSpillLoadStore() local
955 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in buildSGPRSpillLoadStore()
965 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in buildSGPRSpillLoadStore()
966 SuperReg != AMDGPU::EXEC && "exec should never spill"); in buildSGPRSpillLoadStore()
970 bool OnlyExecLo = isWave32 || NumSubRegs == 1 || SuperReg == AMDGPU::EXEC_HI; in buildSGPRSpillLoadStore()
980 ? SuperReg in buildSGPRSpillLoadStore()
981 : Register(getSubReg(SuperReg, SplitParts[FirstPart + ExecLane])); in buildSGPRSpillLoadStore()
986 getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]), AMDGPU::sub0, in buildSGPRSpillLoadStore()
1043 getSubReg(SuperReg, SplitParts[FirstPart + ExecLane + 1])) in buildSGPRSpillLoadStore()
1050 SuperReg, SplitParts[FirstPart + ExecLane]))) in buildSGPRSpillLoadStore()
[all …]
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| D | SIInstrInfo.h | 71 MachineOperand &SuperReg,
77 MachineOperand &SuperReg,
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| D | SIInstrInfo.cpp | 4351 MachineOperand &SuperReg, in buildExtractSubReg() argument
4360 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
4362 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
4373 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 574 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
577 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
578 SuperReg = Reg; in FindSuitableFreeRegisters()
600 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
601 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
616 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
630 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
652 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
663 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
666 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 556 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
559 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
560 SuperReg = Reg; in FindSuitableFreeRegisters()
582 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
583 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
598 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << in FindSuitableFreeRegisters()
612 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
634 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
645 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
648 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
|
| D | ScheduleDAGInstrs.cpp | 1258 const unsigned SuperReg = MO.getReg(); in toggleKillFlag() local
1260 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { in toggleKillFlag()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 569 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
572 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
573 SuperReg = Reg; in FindSuitableFreeRegisters()
595 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
596 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
611 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
625 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
647 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
658 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
661 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 762 Register SuperReg = MI->getOperand(0).getReg(); in spillSGPR() local
768 assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() && in spillSGPR()
769 SuperReg != MFI->getFrameOffsetReg() && in spillSGPR()
770 SuperReg != MFI->getScratchWaveOffsetReg())); in spillSGPR()
772 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in spillSGPR()
775 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in spillSGPR()
788 NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]); in spillSGPR()
832 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState); in spillSGPR()
874 Register SuperReg = MI->getOperand(0).getReg(); in restoreSGPR() local
876 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in restoreSGPR()
[all …]
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| D | SIInstrInfo.h | 71 MachineOperand &SuperReg,
77 MachineOperand &SuperReg,
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| D | SIInstrInfo.cpp | 3863 MachineOperand &SuperReg, in buildExtractSubReg() argument
3872 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
3874 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
3885 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 849 unsigned SuperReg = in copyPhysReg() local
852 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
855 DestReg = SuperReg; in copyPhysReg()
858 unsigned SuperReg = in copyPhysReg() local
861 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
864 DestReg = SuperReg; in copyPhysReg()
867 unsigned SuperReg = in copyPhysReg() local
870 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
873 SrcReg = SuperReg; in copyPhysReg()
876 unsigned SuperReg = in copyPhysReg() local
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 46 MachineOperand &SuperReg,
52 MachineOperand &SuperReg,
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| D | SIRegisterInfo.cpp | 520 unsigned SuperReg = MI->getOperand(0).getReg(); in eliminateFrameIndex() local
525 unsigned SubReg = getPhysRegSubReg(SuperReg, in eliminateFrameIndex()
556 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState); in eliminateFrameIndex()
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| D | SIInstrInfo.cpp | 1903 MachineOperand &SuperReg, in buildExtractSubReg() argument
1912 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
1914 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
1925 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| D | R600InstrInfo.cpp | 1120 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); in reserveIndirectRegisters() local
1121 Reserved.set(SuperReg); in reserveIndirectRegisters()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1930 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1937 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2166 SDValue SuperReg; in SelectVLDSTLane() local
2171 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2173 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2180 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2182 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2184 Ops.push_back(SuperReg); in SelectVLDSTLane()
2200 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2207 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2133 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2140 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2377 SDValue SuperReg; in SelectVLDSTLane() local
2382 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2384 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2391 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2393 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2395 Ops.push_back(SuperReg); in SelectVLDSTLane()
2411 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2418 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1146 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1174 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1176 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1282 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1331 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1334 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
1341 SuperReg); in SelectPostLoadLane()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1373 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1376 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1406 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1408 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1412 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1465 SDValue SuperReg = SDValue(Load, 0); in SelectPredicatedLoad() local
1468 AArch64::zsub0 + i, DL, VT, SuperReg)); in SelectPredicatedLoad()
1617 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1623 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1666 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2183 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2190 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2433 SDValue SuperReg; in SelectVLDSTLane() local
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2440 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2447 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2449 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2451 Ops.push_back(SuperReg); in SelectVLDSTLane()
2467 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2474 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1291 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1294 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1324 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1326 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1330 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1436 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1442 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1485 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1488 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
1495 SuperReg); in SelectPostLoadLane()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 913 MCRegister SuperReg = in copyPhysReg() local
916 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
919 DestReg = SuperReg; in copyPhysReg()
922 MCRegister SuperReg = in copyPhysReg() local
925 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
928 SrcReg = SuperReg; in copyPhysReg()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1255 MCRegister SuperReg = in copyPhysReg() local
1258 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
1261 DestReg = SuperReg; in copyPhysReg()
1264 MCRegister SuperReg = in copyPhysReg() local
1267 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
1270 SrcReg = SuperReg; in copyPhysReg()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6066 unsigned SuperReg = MRI->getMatchingSuperReg( in ParseInstruction() local
6069 assert(SuperReg && "expected register pair"); in ParseInstruction()
6071 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); in ParseInstruction()
|