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Searched refs:TSFlags (Results 1 – 25 of 248) sorted by relevance

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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td139 let TSFlags{0} = SALU;
140 let TSFlags{1} = VALU;
142 let TSFlags{2} = SOP1;
143 let TSFlags{3} = SOP2;
144 let TSFlags{4} = SOPC;
145 let TSFlags{5} = SOPK;
146 let TSFlags{6} = SOPP;
148 let TSFlags{7} = VOP1;
149 let TSFlags{8} = VOP2;
150 let TSFlags{9} = VOPC;
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DSIInstrInfo.h340 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
344 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
348 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
352 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
364 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
368 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
372 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
376 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
380 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
384 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h184 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
188 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
192 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
196 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
212 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
220 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
228 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
83 let TSFlags{9} = isRestrictSlot1AOK;
87 let TSFlags{10} = isPredicated;
89 let TSFlags{11} = isPredicatedFalse;
91 let TSFlags{12} = isPredicatedNew;
93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
97 let TSFlags{14} = isNewValue; // New-value consumer insn.
99 let TSFlags{15} = hasNewValue; // New-value producer insn.
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h334 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
338 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
342 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
346 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
358 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
362 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
366 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
370 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
374 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
378 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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DSIInstrFormats.td131 let TSFlags{0} = SALU;
132 let TSFlags{1} = VALU;
134 let TSFlags{2} = SOP1;
135 let TSFlags{3} = SOP2;
136 let TSFlags{4} = SOPC;
137 let TSFlags{5} = SOPK;
138 let TSFlags{6} = SOPP;
140 let TSFlags{7} = VOP1;
141 let TSFlags{8} = VOP2;
142 let TSFlags{9} = VOPC;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td71 let TSFlags{6-0} = Type.Value;
75 let TSFlags{7} = isSolo;
78 let TSFlags{8} = isSoloAX;
81 let TSFlags{9} = isRestrictSlot1AOK;
85 let TSFlags{10} = isPredicated;
87 let TSFlags{11} = isPredicatedFalse;
89 let TSFlags{12} = isPredicatedNew;
91 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
95 let TSFlags{14} = isNewValue; // New-value consumer insn.
97 let TSFlags{15} = hasNewValue; // New-value producer insn.
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DHexagonInstrFormatsV5.td51 let TSFlags{6-0} = Type.Value;
55 let TSFlags{7} = isPredicated;
57 let TSFlags{8} = isPredicatedFalse;
59 let TSFlags{9} = isPredicatedNew;
63 let TSFlags{10} = isNewValue; // New-value consumer insn.
65 let TSFlags{11} = hasNewValue; // New-value producer insn.
67 let TSFlags{14-12} = opNewValue; // New-value produced operand.
69 let TSFlags{15} = isNVStorable; // Store that can become new-value store.
71 let TSFlags{16} = isNVStore; // New-value store insn.
75 let TSFlags{17} = isExtendable; // Insn may be extended.
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp126 uint64_t TSFlags, bool Rex, unsigned &CurByte,
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
141 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
145 uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
165 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { in isCDisp8() argument
166 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && in isCDisp8()
170 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isCDisp8()
190 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
191 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
192 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
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DX86BaseInfo.h564 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
565 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
568 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
569 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
574 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
575 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
590 inline unsigned isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
591 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
608 inline unsigned isImmSigned(uint64_t TSFlags) { in isImmSigned() argument
609 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp110 uint64_t TSFlags, bool Rex, unsigned &CurByte,
114 void emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, unsigned &CurByte,
118 void emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
125 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
129 uint8_t determineREXPrefix(const MCInst &MI, uint64_t TSFlags, int MemOperand,
141 static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue) { in isCDisp8() argument
142 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && in isCDisp8()
146 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isCDisp8()
166 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
167 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
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DX86ATTInstPrinter.cpp102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
160 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
162 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
166 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
173 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
174 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
175 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
142 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
152 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
153 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
156 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
164 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
165 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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DX86BaseInfo.h905 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
906 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
909 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
910 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
915 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
916 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
932 inline bool isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
933 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
951 inline bool isImmSigned(uint64_t TSFlags) { in isImmSigned() argument
952 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
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/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp79 uint64_t TSFlags, bool HasREX, uint64_t StartByte,
119 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8() argument
120 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
123 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isDispOrCDisp8()
142 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
143 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
144 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
146 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
257 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4) in isPCRel32Branch()
379 uint64_t TSFlags, bool HasREX, in emitMemModRMByte() argument
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DX86ATTInstPrinter.cpp102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
160 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
162 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
166 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
173 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
174 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
175 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
142 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
152 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
153 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
156 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
164 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
165 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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DX86BaseInfo.h963 inline bool isPrefix(uint64_t TSFlags) { in isPrefix() argument
964 return (TSFlags & X86II::FormMask) == PrefixByte; in isPrefix()
968 inline bool isPseudo(uint64_t TSFlags) { in isPseudo() argument
969 return (TSFlags & X86II::FormMask) == Pseudo; in isPseudo()
974 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
975 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
978 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
979 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
984 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
985 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td50 let TSFlags{3-0} = VecInstType;
51 let TSFlags{4-4} = IsSimpleMove;
52 let TSFlags{5-5} = IsLoad;
53 let TSFlags{6-6} = IsStore;
54 let TSFlags{7} = IsTex;
55 let TSFlags{9-8} = IsSuld;
56 let TSFlags{10} = IsSust;
57 let TSFlags{11} = IsSurfTexQuery;
58 let TSFlags{12} = IsTexModeUnified;
DNVPTXInstrInfo.cpp73 unsigned TSFlags = in isMoveInstr() local
74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; in isMoveInstr()
75 isMove = (TSFlags == 1); in isMoveInstr()
94 unsigned TSFlags = in isLoadInstr() local
95 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; in isLoadInstr()
96 isLoad = (TSFlags == 1); in isLoadInstr()
105 unsigned TSFlags = in isStoreInstr() local
106 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift; in isStoreInstr()
107 isStore = (TSFlags == 1); in isStoreInstr()
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td49 let TSFlags{3...0} = VecInstType;
50 let TSFlags{4...4} = IsSimpleMove;
51 let TSFlags{5...5} = IsLoad;
52 let TSFlags{6...6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9...8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td49 let TSFlags{3-0} = VecInstType;
50 let TSFlags{4-4} = IsSimpleMove;
51 let TSFlags{5-5} = IsLoad;
52 let TSFlags{6-6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9-8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV4.td64 let TSFlags{4-0} = Type.Value;
68 let TSFlags{6} = isPredicated;
70 let TSFlags{7} = isPredicatedFalse;
72 let TSFlags{8} = isPredicatedNew;
76 let TSFlags{9} = isNewValue; // New-value consumer insn.
78 let TSFlags{10} = hasNewValue; // New-value producer insn.
80 let TSFlags{13-11} = opNewValue; // New-value produced operand.
82 let TSFlags{14} = isNVStorable; // Store that can become new-value store.
84 let TSFlags{15} = isNVStore; // New-value store insn.
88 let TSFlags{16} = isExtendable; // Insn may be extended.
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/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp236 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
243 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
311 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
329 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
335 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
341 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
399 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
418 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
508 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp211 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
218 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
286 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
304 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
310 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
316 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
349 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
393 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
463 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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