| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_overlap_add1.s | 95 UMULL V15.4S, V7.4H, V2.4H
97 USHR V15.4S, V15.4S, #16
99 SMLAL V15.4S, V6.4H, V2.4H
100 SQSHL V15.4S, V15.4S, V11.4S
109 SQSUB V13.4S, V15.4S, V14.4S
153 UMULL V15.4S, V7.4H, V2.4H
157 USHR V15.4S, V15.4S, #16
161 SMLAL V15.4S, V6.4H, V2.4H
165 SQSHL V15.4S, V15.4S, V11.4S
200 SQSUB V13.4S, V15.4S, V14.4S
[all …]
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| D | ixheaacd_sbr_imdct_using_fft.s | 169 LD2 {V14.S, V15.S}[0], [X5] , X1
181 LD2 {V14.S, V15.S}[1], [X6] , X1
190 LD2 {V14.S, V15.S}[2], [X7] , X1
199 LD2 {V14.S, V15.S}[3], [X11] , X1
218 ADD V14.4S, V15.4S, V13.4S
222 SUB V12.4S, V15.4S, V13.4S
224 ADD V15.4S, V10.4S, V1.4S
229 ADD V11.4S, V17.4S, V15.4S
230 SUB V2.4S, V17.4S, V15.4S
232 SUB V15.4S, V14.4S, V10.4S
[all …]
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| D | ixheaacd_overlap_add2.s | 85 LD2 {V14.4H, V15.4H}, [X7], X12
87 REV64 V13.4H, V15.4H
120 LD2 {V14.4H, V15.4H}, [X7], X12
123 REV64 V13.4H, V15.4H
|
| /external/antlr/runtime/JavaScript/tests/functional/ |
| D | t053heteroTP15.g | 10 function V15(ttype) {
11 V15.superclass.constructor.call(this, new org.antlr.runtime.CommonToken(ttype));
13 org.antlr.lang.extend(V15, org.antlr.runtime.tree.CommonTree, {
19 a : ID -> ROOT<V15> ID
|
| /external/llvm/test/MC/Hexagon/ |
| D | v60lookup.s | 5 V31.b = vlut32(V29.b, V15.b, R1)
7 V31.b |= vlut32(V29.b, V15.b, R2)
9 V31:30.h = vlut16(V29.b, V15.h, R3)
|
| /external/llvm-project/llvm/test/MC/Hexagon/ |
| D | v60lookup.s | 5 V31.b = vlut32(V29.b, V15.b, R1)
7 V31.b |= vlut32(V29.b, V15.b, R2)
9 V31:30.h = vlut16(V29.b, V15.h, R3)
|
| /external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/ |
| D | fuchsia-multiple-inheritance.cpp | 119 struct V15 : virtual Base6 { virtual void f() = 0; }; struct
123 struct D9 : V15, V16 {};
|
| /external/llvm-project/clang/test/CodeGenObjC/ |
| D | os_log.m | 48 // CHECK-O2: %[[V15:.*]] = load i8*, i8** %[[A_ADDR]], align 8
49 // CHECK-O2: call void @llvm.objc.release(i8* %[[V15]])
118 // CHECK-O2: %[[V15:.*]] = load i8*, i8** %[[OS_LOG_ARG]], align 8
119 // CHECK-O2: call void @llvm.objc.release(i8* %[[V15]])
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 86 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
100 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
|
| D | HexagonRegisterInfo.cpp | 70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/ |
| D | smlad11.ll | 9 ; CHECK: [[V15:%[0-9]+]] = bitcast i16* %arrayidx4 to i32*
10 ; CHECK: [[V16:%[0-9]+]] = load i32, i32* [[V15]], align 2
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
|
| D | HexagonRegisterInfo.cpp | 70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
|
| D | HexagonRegisterInfo.td | 214 def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>;
234 def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>;
|
| /external/llvm-project/mlir/test/Dialect/SCF/ |
| D | parallel-loop-tiling.mlir | 108 // CHECK: scf.parallel ([[V15:%.*]], [[V16:%.*]]) = ([[C0_2]], [[C0_2]]) to ([[V10]], […
109 // CHECK: = addi [[V15]], [[V12]] : index
|
| /external/llvm-project/llvm/test/Bitcode/ |
| D | upgrade-arc-runtime-calls.ll | 84 // ARC-NEXT: %[[V15:.*]] = tail call i8* @llvm.objc.unretainedPointer(i8* %[[A]])
117 // NOUPGRADE-NEXT: %[[V15:.*]] = tail call i8* @objc_unretainedPointer(i8* %[[A]])
|
| /external/libchrome/mojo/public/interfaces/bindings/tests/ |
| D | test_structs.mojom | 215 const int64 V15 = -9007199254740991; // Number.MIN_SAFE_INTEGER
239 int64 f15 = V15;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 71 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
|
| D | HexagonRegisterInfo.td | 190 def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>;
275 V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.cpp | 105 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
|
| /external/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.cpp | 106 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.cpp | 106 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
|
| /external/llvm-project/mlir/test/Dialect/LLVMIR/ |
| D | roundtrip.mlir | 162 // CHECK: %[[V15:.*]] = llvm.insertvalue %[[V5]], %[[V14]][0] : !llvm.struct<(i32, double, i32)>
163 // CHECK: %[[V16:.*]] = llvm.insertvalue %[[V7]], %[[V15]][1] : !llvm.struct<(i32, double, i32)>
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | extract_vector_dynelt.ll | 363 ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V15:v[0-9]+]], {{[^,]+}}, [[V14]], [[C15]]
364 ; GCN: store_byte v[{{[0-9:]+}}], [[V15]]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenRegisterInfo.inc | 186 V15 = 166,
1566 …, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17…
1576 …, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17…
1596 …, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17…
1616 …, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17…
2482 { PPC::V15, 92U },
2757 { PPC::V15, 92U },
3035 { PPC::V15, 92U },
3310 { PPC::V15, 92U },
5740 …, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17…
[all …]
|