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Searched refs:VEX_4V (Results 1 – 24 of 24) sorted by relevance

/external/llvm-project/llvm/lib/Target/X86/
DX86InstrAMX.td64 VEX_4V, T8XD;
68 VEX_4V, T8XS;
72 VEX_4V, T8PD;
76 VEX_4V, T8PS;
108 []>, VEX_4V, T8XS;
DX86InstrSSE.td216 VEX_4V, VEX_LIG, VEX_WIG;
643 VEX_4V, VEX_WIG;
783 VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG;
790 VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG,
902 WriteCvtI2SS, SSEPackedSingle>, XS, VEX_4V,
905 WriteCvtI2SS, SSEPackedSingle>, XS, VEX_4V,
908 WriteCvtI2SD, SSEPackedDouble>, XD, VEX_4V,
911 WriteCvtI2SD, SSEPackedDouble>, XD, VEX_4V,
1051 XS, VEX_4V, VEX_LIG, SIMD_EXC;
1054 XS, VEX_4V, VEX_LIG, VEX_W, SIMD_EXC;
[all …]
DX86InstrFormats.td225 class VEX_4V : VEX { bit hasVEX_4V = 1; }
901 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>;
905 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>;
909 VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>;
915 VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>;
919 VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>;
923 VEX_4V, FMASC, Requires<[HasFMA4]>;
946 VEX_4V, Requires<[HasXOP]>;
DX86InstrArithmetic.td1455 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V;
1456 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, VEX_W;
1478 []>, T8XD, VEX_4V, Sched<[sched, WriteIMulH]>;
1484 []>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>;
DX86InstrInfo.td2489 T8PS, VEX_4V, Sched<[sched]>;
2493 T8PS, VEX_4V, Sched<[sched.Folded]>;
2655 VEX_4V, Sched<[WriteALU]>;
2659 VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
DX86MCInstLower.cpp966 !(TSFlags & X86II::VEX_W) && (TSFlags & X86II::VEX_4V) && in Lower()
DX86InstrAVX512.td3033 sched, HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
3035 sched, prdW, IsCommutable>, VEX_4V, VEX_L, PS;
3037 sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
3039 sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
3094 VEX_4V, VEX_L, Sched<[sched]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrSSE.td216 VEX_4V, VEX_LIG, VEX_WIG;
643 VEX_4V, VEX_WIG;
793 VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG;
800 VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG,
895 WriteCvtI2SS, SSEPackedSingle>, XS, VEX_4V,
898 WriteCvtI2SS, SSEPackedSingle>, XS, VEX_4V,
901 WriteCvtI2SD, SSEPackedDouble>, XD, VEX_4V,
904 WriteCvtI2SD, SSEPackedDouble>, XD, VEX_4V,
1014 XS, VEX_4V, VEX_LIG, SIMD_EXC;
1017 XS, VEX_4V, VEX_LIG, VEX_W, SIMD_EXC;
[all …]
DX86InstrFormats.td217 class VEX_4V : VEX { bit hasVEX_4V = 1; }
888 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>;
892 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>;
896 VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>;
902 VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>;
906 VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>;
910 VEX_4V, FMASC, Requires<[HasFMA4]>;
933 VEX_4V, Requires<[HasXOP]>;
DX86InstrArithmetic.td1288 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V;
1289 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, VEX_W;
1312 []>, T8XD, VEX_4V, Sched<[sched, WriteIMulH]>;
1317 []>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>;
DX86InstrInfo.td2423 T8PS, VEX_4V, Sched<[sched]>;
2427 T8PS, VEX_4V, Sched<[sched.Folded]>;
2589 VEX_4V, Sched<[WriteALU]>;
2593 VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
DX86MCInstLower.cpp919 !(TSFlags & X86II::VEX_W) && (TSFlags & X86II::VEX_4V) && in Lower()
DX86InstrAVX512.td3002 sched, HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
3004 sched, prdW, IsCommutable>, VEX_4V, VEX_L, PS;
3006 sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
3008 sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
3065 VEX_4V, VEX_L, Sched<[sched]>;
/external/llvm/lib/Target/X86/
DX86InstrSSE.td536 VEX_4V, VEX_LIG;
1134 itin>, VEX_4V;
1358 VEX_4V, Sched<[WriteFShuffle]>;
1365 VEX_4V, Sched<[WriteFShuffle]>;
1520 XS, VEX_4V, VEX_LIG;
1522 XS, VEX_4V, VEX_W, VEX_LIG;
1524 XD, VEX_4V, VEX_LIG;
1526 XD, VEX_4V, VEX_W, VEX_LIG;
1655 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1658 SSE_CVT_Scalar, 0>, XS, VEX_4V,
[all …]
DX86InstrFormats.td192 class VEX_4V : VEX { bit hasVEX_4V = 1; }
198 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
842 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
848 VEX_4V, FMASC, Requires<[HasFMA, NoVLX]>;
854 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
872 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
DX86InstrArithmetic.td1283 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1284 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
1306 [], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
1311 [], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
DX86InstrInfo.td2211 []>, T8PS, VEX_4V;
2215 []>, T8PS, VEX_4V;
2328 VEX_4V;
2331 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
DX86InstrAVX512.td2266 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2268 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2270 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2272 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2364 VEX_4V, VEX_L;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp604 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in EmitVEXOpcodePrefix()
659 uint8_t VEX_4V = 0xf; in EmitVEXOpcodePrefix() local
734 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
762 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
779 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; in EmitVEXOpcodePrefix()
791 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
822 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
833 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; in EmitVEXOpcodePrefix()
858 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
877 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h489 VEX_4V = 1ULL << VEX_4VShift, enumerator
660 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in getMemoryOperandNo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp747 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in emitVEXOpcodePrefix()
813 uint8_t VEX_4V = 0xf; in emitVEXOpcodePrefix() local
894 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
921 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
947 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; in emitVEXOpcodePrefix()
956 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
978 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
1012 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
1040 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; in emitVEXOpcodePrefix()
1049 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h865 VEX_4V = 1ULL << VEX_4VShift, enumerator
1016 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in getMemoryOperandNo()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp766 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in emitVEXOpcodePrefix()
832 uint8_t VEX_4V = 0xf; in emitVEXOpcodePrefix() local
916 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
944 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
970 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; in emitVEXOpcodePrefix()
979 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
1001 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
1035 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
1063 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; in emitVEXOpcodePrefix()
1072 VEX_4V = ~VRegEnc & 0xf; in emitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h920 VEX_4V = 1ULL << VEX_4VShift, enumerator
1085 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in getMemoryOperandNo()