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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dstack-realign-kernel.ll1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
7 ; VI-LABEL: max_alignment_128:
8 ; VI: ; %bb.0:
9 ; VI-NEXT: s_add_u32 s4, s4, s7
10 ; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
11 ; VI-NEXT: s_add_u32 s0, s0, s7
12 ; VI-NEXT: s_addc_u32 s1, s1, 0
13 ; VI-NEXT: v_mov_b32_e32 v0, 9
14 ; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
15 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
[all …]
Dimm.ll3 …-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
18 ; VI-LABEL: i64_imm_inline_lo:
19 ; VI: ; %bb.0: ; %entry
20 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
21 ; VI-NEXT: s_mov_b32 s3, 0xf000
22 ; VI-NEXT: s_mov_b32 s2, -1
23 ; VI-NEXT: v_mov_b32_e32 v0, 5
24 ; VI-NEXT: v_mov_b32_e32 v1, 0x12345678
25 ; VI-NEXT: s_waitcnt lgkmcnt(0)
26 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
[all …]
Dllvm.amdgcn.ubfe.ll3 …cpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VI %s
18 ; VI-LABEL: bfe_u32_arg_arg_arg:
19 ; VI: ; %bb.0:
20 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
21 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
22 ; VI-NEXT: s_mov_b32 s7, 0xf000
23 ; VI-NEXT: s_mov_b32 s6, -1
24 ; VI-NEXT: s_waitcnt lgkmcnt(0)
25 ; VI-NEXT: v_mov_b32_e32 v0, s0
26 ; VI-NEXT: v_bfe_u32 v0, v0, s1, s1
[all …]
Dinsert_vector_elt.ll3 …+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s
28 ; VI-LABEL: insertelement_v4f32_0:
29 ; VI: ; %bb.0:
30 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
31 ; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
32 ; VI-NEXT: s_waitcnt lgkmcnt(0)
33 ; VI-NEXT: s_mov_b32 s4, 0x40a00000
34 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
35 ; VI-NEXT: s_mov_b32 s2, -1
36 ; VI-NEXT: v_mov_b32_e32 v0, s4
[all …]
Dwiden-smrd-loads.ll3 …dgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
22 ; VI-LABEL: widen_i16_constant_load:
23 ; VI: ; %bb.0:
24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
25 ; VI-NEXT: v_mov_b32_e32 v0, 0
26 ; VI-NEXT: v_mov_b32_e32 v1, 0
27 ; VI-NEXT: s_waitcnt lgkmcnt(0)
28 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
29 ; VI-NEXT: s_waitcnt lgkmcnt(0)
30 ; VI-NEXT: s_addk_i32 s0, 0x3e7
[all …]
Dcopy-illegal-type.ll3 … | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
27 ; VI-LABEL: test_copy_v4i8:
28 ; VI: ; %bb.0:
29 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
30 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
31 ; VI-NEXT: s_mov_b32 s3, 0xf000
32 ; VI-NEXT: s_mov_b32 s2, -1
33 ; VI-NEXT: s_waitcnt lgkmcnt(0)
34 ; VI-NEXT: v_mov_b32_e32 v1, s7
35 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
[all …]
Dmax.i16.ll2 …iji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,VI
7 ; VI-LABEL: v_test_imax_sge_i16:
8 ; VI: ; %bb.0:
9 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
10 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
11 ; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0
12 ; VI-NEXT: s_waitcnt lgkmcnt(0)
13 ; VI-NEXT: v_mov_b32_e32 v1, s7
14 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
15 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
[all …]
Dsub.v2i16.ll3 …for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,GFX89,VI
24 ; VI-LABEL: v_test_sub_v2i16:
25 ; VI: ; %bb.0:
26 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
27 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
28 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
29 ; VI-NEXT: s_waitcnt lgkmcnt(0)
30 ; VI-NEXT: v_mov_b32_e32 v1, s7
31 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
32 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
[all …]
Dselect.f16.ll3 …cn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
47 ; VI-LABEL: select_f16:
48 ; VI: ; %bb.0: ; %entry
49 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
50 ; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
51 ; VI-NEXT: s_mov_b32 s3, 0xf000
52 ; VI-NEXT: s_mov_b32 s2, -1
53 ; VI-NEXT: s_mov_b32 s18, s2
54 ; VI-NEXT: s_waitcnt lgkmcnt(0)
55 ; VI-NEXT: s_mov_b32 s16, s6
[all …]
Damdgpu-codegenprepare-i16-to-i32.ll3 ; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI …
11 ; VI-LABEL: @add_i3(
12 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
13 ; VI-NEXT: [[TMP2:%.*]] = zext i3 [[B:%.*]] to i32
14 ; VI-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP2]]
15 ; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i3
16 ; VI-NEXT: store volatile i3 [[TMP4]], i3 addrspace(1)* undef
17 ; VI-NEXT: ret void
30 ; VI-LABEL: @add_nsw_i3(
31 ; VI-NEXT: [[TMP1:%.*]] = zext i3 [[A:%.*]] to i32
[all …]
Dsign_extend.ll3 …neinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,VI
19 ; VI-LABEL: s_sext_i1_to_i32:
20 ; VI: ; %bb.0:
21 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
22 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
23 ; VI-NEXT: s_mov_b32 s7, 0xf000
24 ; VI-NEXT: s_mov_b32 s6, -1
25 ; VI-NEXT: s_waitcnt lgkmcnt(0)
26 ; VI-NEXT: v_mov_b32_e32 v0, s1
27 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0
[all …]
Dcvt_f32_ubyte.ll3 …mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VI
67 ; VI-LABEL: v_uitofp_to_f32_multi_use_lshr8_mask255:
68 ; VI: ; %bb.0:
69 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
70 ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
71 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
72 ; VI-NEXT: s_mov_b32 s7, 0xf000
73 ; VI-NEXT: s_mov_b32 s6, -1
74 ; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
75 ; VI-NEXT: s_waitcnt vmcnt(0)
[all …]
Dfmin_legacy.f64.ll3 ; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
27 ; VI-LABEL: test_fmin_legacy_uge_f64:
28 ; VI: ; %bb.0:
29 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
30 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
31 ; VI-NEXT: s_waitcnt lgkmcnt(0)
32 ; VI-NEXT: v_mov_b32_e32 v1, s3
33 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
34 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
35 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
[all …]
Dbswap.ll3 …mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=FUNC,GCN,VI
34 ; VI-LABEL: test_bswap_i32:
35 ; VI: ; %bb.0:
36 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
37 ; VI-NEXT: v_mov_b32_e32 v0, 0x10203
38 ; VI-NEXT: s_mov_b32 s7, 0xf000
39 ; VI-NEXT: s_mov_b32 s6, -1
40 ; VI-NEXT: s_waitcnt lgkmcnt(0)
41 ; VI-NEXT: s_mov_b32 s4, s0
42 ; VI-NEXT: s_load_dword s0, s[2:3], 0x0
[all …]
Dv_madak_f16.ll3 …cn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
32 ; VI-LABEL: madak_f16:
33 ; VI: ; %bb.0: ; %entry
34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
35 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
36 ; VI-NEXT: s_mov_b32 s3, 0xf000
37 ; VI-NEXT: s_mov_b32 s2, -1
38 ; VI-NEXT: s_mov_b32 s10, s2
39 ; VI-NEXT: s_waitcnt lgkmcnt(0)
40 ; VI-NEXT: s_mov_b32 s0, s4
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dirtranslator-amdgpu_kernel.ll2 …uments=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck -check-prefix=HSA-VI %s
3 … -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck -check-prefix=LEGACY-MESA-VI %s
6 ; HSA-VI-LABEL: name: i8_arg
7 ; HSA-VI: bb.1 (%ir-block.0):
8 ; HSA-VI: liveins: $sgpr4_sgpr5
9 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
10 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
11 ; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
12 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, …
13 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
[all …]
Dllvm.amdgcn.rsq.clamp.ll3 …c -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
12 ; VI-LABEL: v_rsq_clamp_f32:
13 ; VI: ; %bb.0:
14 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15 ; VI-NEXT: v_rsq_f32_e32 v0, v0
16 ; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0
17 ; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0
18 ; VI-NEXT: s_setpc_b64 s[30:31]
30 ; VI-LABEL: v_rsq_clamp_fabs_f32:
31 ; VI: ; %bb.0:
[all …]
Dfrem.ll3 …isched=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
42 ; VI-LABEL: frem_f16:
43 ; VI: ; %bb.0:
44 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
45 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
46 ; VI-NEXT: s_waitcnt lgkmcnt(0)
47 ; VI-NEXT: v_mov_b32_e32 v0, s6
48 ; VI-NEXT: s_add_u32 s0, s8, 8
49 ; VI-NEXT: v_mov_b32_e32 v1, s7
50 ; VI-NEXT: s_addc_u32 s1, s9, 0
[all …]
Dcvt_f32_ubyte.ll3 …isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
16 ; VI-LABEL: v_uitofp_i32_to_f32_mask255:
17 ; VI: ; %bb.0:
18 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19 ; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
20 ; VI-NEXT: s_setpc_b64 s[30:31]
34 ; VI-LABEL: v_sitofp_i32_to_f32_mask255:
35 ; VI: ; %bb.0:
36 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
37 ; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
[all …]
Dlegalize-store.mir3 …a3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
14 ; VI-LABEL: name: test_store_global_i32
15 ; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
16 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
17 ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
33 ; VI-LABEL: name: test_store_global_i64
34 ; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
35 ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
36 ; VI: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store 8, addrspace 1)
52 ; VI-LABEL: name: test_store_global_p1
[all …]
Dlegalize-zextload-flat.mir3 …e=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI
14 ; VI-LABEL: name: test_zextload_flat_i32_i8
15 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
16 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
17 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
18 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
19 ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
20 ; VI: $vgpr0 = COPY [[AND]](s32)
35 ; VI-LABEL: name: test_zextload_flat_i32_i16
36 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
[all …]
Dllvm.amdgcn.atomic.inc.ll3 …dhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
36 ; VI-LABEL: lds_atomic_inc_ret_i32:
37 ; VI: ; %bb.0:
38 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
39 ; VI-NEXT: s_load_dword s2, s[4:5], 0x8
40 ; VI-NEXT: v_mov_b32_e32 v0, 42
41 ; VI-NEXT: s_mov_b32 m0, -1
42 ; VI-NEXT: s_waitcnt lgkmcnt(0)
43 ; VI-NEXT: v_mov_b32_e32 v1, s2
44 ; VI-NEXT: ds_inc_rtn_u32 v2, v1, v0
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dvop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
6 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
9 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
12 # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
15 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
18 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
21 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
24 # VI: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
27 # VI: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
[all …]
Dsop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
6 # VI: s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]
9 # VI: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x00,0x81,0xbe,0x64,0x00,0x00,0x00]
12 # VI: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x00,0x81,0xbe,0x00,0x00,0x00,0x80]
15 # VI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x00,0x80,0xbe,0xab,0x63,0x51,0xfe]
18 # VI: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
21 # VI: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
24 # VI: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x01,0x82,0xbe]
27 # VI: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x01,0x82,0xbe]
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
6 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
9 # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
12 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
15 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
18 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
21 # VI: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
24 # VI: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
27 # VI: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
[all …]

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