| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrTDX.td | 19 // SEAMCALL - Call to SEAM VMX-root Operation Module
23 // SEAMRET - Return to Legacy VMX-root Operation
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| D | X86InstrVMX.td | 1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
9 // This file describes the instructions that make up the Intel VMX instruction
15 // VMX instructions
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| /external/linux-kselftest/tools/testing/selftests/powerpc/math/ |
| D | vsx_asm.S | 26 # that the VMX have been loaded with varray. Will proceed to check the
27 # validity of the VMX registers while running is not zero.
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| D | vmx_asm.S | 114 # the VMX have been loaded with varray. Will proceed to check the validity of
115 # the VMX registers while running is not zero.
121 # VMX need to write to 16 byte aligned addresses, skip STACK_FRAME_LOCAL(3,0)
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrVMX.td | 1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
10 // This file describes the instructions that make up the Intel VMX instruction
16 // VMX instructions
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrVMX.td | 1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
9 // This file describes the instructions that make up the Intel VMX instruction
15 // VMX instructions
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-i128-abi.ll | 17 ; VMX (no VSX):
55 ; VMX (no VSX):
82 ; Little Endian (VSX and VMX):
88 ; Big Endian (VSX and VMX)
118 ; Little Endian (VSX and VMX):
126 ; Big Endian (VSX and VMX):
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| D | vec_add_sub_doubleword.ll | 1 ; Check VMX 64-bit integer operations
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| D | vec_popcnt.ll | 2 ; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8.
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| D | vec_add_sub_quadword.ll | 1 ; Check VMX 128-bit integer operations
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrInfo.cpp | 827 Register VMX = VMXl; in expandPostRAPseudo() local
829 VMX = VMXu; in expandPostRAPseudo()
837 .addDef(VMX) in expandPostRAPseudo()
843 .addDef(VMX) in expandPostRAPseudo()
851 .addDef(VMX) in expandPostRAPseudo()
854 .addReg(VMX); in expandPostRAPseudo()
860 .addDef(VMX) in expandPostRAPseudo()
863 .addReg(VMX); in expandPostRAPseudo()
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-i128-abi.ll | 43 ; VMX (no VSX):
91 ; VMX (no VSX):
118 ; Little Endian (VSX and VMX):
124 ; Big Endian (VSX and VMX)
154 ; Little Endian (VSX and VMX):
162 ; Big Endian (VSX and VMX):
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| D | vec_popcnt.ll | 2 ; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8.
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| D | vec_add_sub_doubleword.ll | 5 ; Check VMX 64-bit integer operations
|
| D | vec_add_sub_quadword.ll | 5 ; Check VMX 128-bit integer operations
|
| /external/llvm-project/lldb/source/Plugins/Process/Linux/ |
| D | NativeRegisterContextLinux_ppc64le.h | 92 VMX m_vmx_ppc64le; // VMX registers.
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| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | RegisterInfos_ppc64le.h | 16 #define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR))
18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
391 } VMX; typedef
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| D | RegisterContextFreeBSD_powerpc.cpp | 169 } VMX; typedef
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| D | RegisterInfos_powerpc.h | 14 #define VMX_OFFSET(regname) (offsetof(VMX, regname))
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP8.td | 41 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
45 // In contrast to the P7, the VMX units on P8 are symmetric, so no need to
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP8.td | 41 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
45 // In contrast to the P7, the VMX units on P8 are symmetric, so no need to
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| D | PPCInstrVSX.td | 15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1812 2. Shift in the VMX register so that the correct doubleword is correctly
1836 // - Now that we set up the shift amount, we shift in the VMX register
1869 // - Now that we set up the shift amount, we shift in the VMX register
1899 // - Now that we set up the shift amount, we shift in the VMX register
1929 // - Now that we set up the shift amount, we shift in the VMX register
1959 - The shift in the VMX register is by 0/8 for opposite element numbers so
1977 - The shift in the VMX register is by 0/8 for opposite element numbers so
1996 - The shift in the VMX register happens for opposite element numbers
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP8.td | 42 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
46 // In contrast to the P7, the VMX units on P8 are symmetric, so no need to
|
| D | PPCInstrVSX.td | 16 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
24 // ** When adding new VMX and VSX instructions, please consider whether they **
1364 2. Shift in the VMX register so that the correct doubleword is correctly
1388 // - Now that we set up the shift amount, we shift in the VMX register
1420 // - Now that we set up the shift amount, we shift in the VMX register
1449 // - Now that we set up the shift amount, we shift in the VMX register
1478 // - Now that we set up the shift amount, we shift in the VMX register
1507 - The shift in the VMX register is by 0/8 for opposite element numbers so
1525 - The shift in the VMX register is by 0/8 for opposite element numbers so
1543 - The shift in the VMX register happens for opposite element numbers
[all …]
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| /external/fec/ |
| D | README | 45 and IBM calls it "VMX". Altivec is roughly comparable to SSE2 on the
|