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Searched refs:Vd (Results 1 – 25 of 183) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMInstrNEON.td275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
DARMInstrFormats.td2078 bits<5> Vd;
2082 let Inst{22} = Vd{4};
2083 let Inst{15-12} = Vd{3-0};
2148 bits<5> Vd;
2151 let Inst{15-12} = Vd{3-0};
2152 let Inst{22} = Vd{4};
2174 bits<5> Vd;
2177 let Inst{15-12} = Vd{3-0};
2178 let Inst{22} = Vd{4};
2188 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
DARMInstrCDE.td299 iname#"\t$coproc, $Vd, $imm", params.Cstr> {
313 bits<5> Vd;
315 let Inst{22} = Vd{0};
316 let Inst{15-12} = Vd{4-1};
323 bits<5> Vd;
325 let Inst{22} = Vd{4};
326 let Inst{15-12} = Vd{3-0};
360 iname#"\t$coproc, $Vd, $Vm, $imm", params.Cstr> {
374 bits<5> Vd;
377 let Inst{15-12} = Vd{4-1};
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DARMInstrFormats.td2227 bits<5> Vd;
2231 let Inst{22} = Vd{4};
2232 let Inst{15-12} = Vd{3-0};
2297 bits<5> Vd;
2300 let Inst{15-12} = Vd{3-0};
2301 let Inst{22} = Vd{4};
2323 bits<5> Vd;
2326 let Inst{15-12} = Vd{3-0};
2327 let Inst{22} = Vd{4};
2337 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
DARMInstrFormats.td2218 bits<5> Vd;
2222 let Inst{22} = Vd{4};
2223 let Inst{15-12} = Vd{3-0};
2288 bits<5> Vd;
2291 let Inst{15-12} = Vd{3-0};
2292 let Inst{22} = Vd{4};
2314 bits<5> Vd;
2317 let Inst{15-12} = Vd{3-0};
2318 let Inst{22} = Vd{4};
2328 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
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/external/llvm-project/clang/include/clang/Analysis/Analyses/
DThreadSafetyTIL.h379 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
380 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
381 Flags = Vd.kind(); in Variable()
666 Function(Variable *Vd, SExpr *Bd) in Function() argument
667 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
668 Vd->setKind(Variable::VK_Fun); in Function()
671 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
672 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
673 Vd->setKind(Variable::VK_Fun); in Function()
717 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
[all …]
/external/clang/include/clang/Analysis/Analyses/
DThreadSafetyTIL.h364 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
365 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
366 Flags = Vd.kind(); in Variable()
659 Function(Variable *Vd, SExpr *Bd) in Function() argument
660 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
661 Vd->setKind(Variable::VK_Fun); in Function()
663 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
664 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
665 Vd->setKind(Variable::VK_Fun); in Function()
710 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
[all …]
/external/llvm-project/clang/lib/Analysis/
DThreadSafety.cpp260 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl()
262 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
294 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
297 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd,
300 void checkBeforeAfter(const ValueDecl* Vd,
1069 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument
1076 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd]; in insertAttrExprs()
1082 for (const auto *At : Vd->attrs()) { in insertAttrExprs()
1110 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1124 BeforeSet::getBeforeInfoForDecl(const ValueDecl *Vd, in getBeforeInfoForDecl() argument
[all …]
/external/clang/lib/Analysis/
DThreadSafety.cpp243 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl()
245 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
275 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
278 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd,
281 void checkBeforeAfter(const ValueDecl* Vd,
967 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument
974 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd]; in insertAttrExprs()
980 for (Attr* At : Vd->attrs()) { in insertAttrExprs()
1008 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1022 BeforeSet::getBeforeInfoForDecl(const ValueDecl *Vd, in getBeforeInfoForDecl() argument
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc1623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
[all …]
DARMGenMCCodeEmitter.inc8296 // op: Vd
8308 // op: Vd
8341 // op: Vd
8353 // op: Vd
8371 // op: Vd
8393 // op: Vd
8421 // op: Vd
8438 // op: Vd
8456 // op: Vd
8473 // op: Vd
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/external/exoplayer/tree/testdata/src/test/assets/amr/
Dsample_nb.amr25 ���g�q���/�fg�r��Vd.�����v��S�˳��,�O~�9;������)��o�Cc��q� ���QAA��qտ��X�C��q��ϐ��p�[g…
Dsample_nb_cbr.amr25 ���g�q���/�fg�r��Vd.�����v��S�˳��,�O~�9;������)��o�Cc��q� ���QAA��qտ��X�C��q��ϐ��p�[g…
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2849 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2850 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2851 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2852 (NOTv16i8 V128:$Vd, V128:$Vn)>;
4018 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4021 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4024 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
4027 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
4030 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
4033 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td502 // maps Vd = #0 to Vd = vxor(Vd, Vd)
503 def : InstAlias<"$Vd = #0",
504 (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
/external/python/cryptography/vectors/cryptography_vectors/x509/PKITS_data/smime/
DSignedValidRFC822nameConstraintsTest25.eml58 Vd+W+ZOlGUPk8Ag1yGqnl0gmKXycSTR5uAAQvzwEz9QM2ZOMWF4N7WVEZMzm1mtZ
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3935 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3936 (NOTv8i8 V64:$Vd, V64:$Vn)>;
3937 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
3938 (NOTv16i8 V128:$Vd, V128:$Vn)>;
5226 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
5229 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
5232 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
5235 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
5238 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
5241 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
[all …]
DAArch64InstrFormats.td6113 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
6114 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
6115 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
6116 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
6118 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
6119 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
6120 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
6121 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
6122 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
6123 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3745 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3746 (NOTv8i8 V64:$Vd, V64:$Vn)>;
3747 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
3748 (NOTv16i8 V128:$Vd, V128:$Vn)>;
4993 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4996 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4999 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
5002 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
5005 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
5008 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
[all …]
DAArch64InstrFormats.td5936 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
5937 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
5938 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
5939 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
5941 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
5942 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
5943 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
5944 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5945 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
5946 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
/external/capstone/arch/ARM/
DARMDisassembler.c1297 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); in DecodeSPRRegListOperand() local
1301 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1302 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1307 if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1310 if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1322 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); in DecodeDPRRegListOperand() local
1326 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1327 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1333 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1337 if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dcde-fp-vec.txt30 # Vector variant, Vd<0> == 1
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1249 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1253 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1254 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1273 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1278 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]

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